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Xeon Gold 5218N - Intel
| Edit Values | |
| General Info | |
| Microarchitecture |
Xeon Gold 5218N is a 64-bit 16-core x86 high performance server microprocessor introduced by Intel in early 2019. The Gold 5218N is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 4-way multiprocessing, sports one AVX-512 FMA units as well as three UPI links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2666 memory, operates at 2.3 GHz with a TDP of 105 W and features a turbo boost frequency of up to 3.7 GHz.
Facts about "Xeon Gold 5218N - Intel"
| base frequency | 2,300 MHz (2.3 GHz, 2,300,000 kHz) + |
| bus links | 4 + |
| bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
| bus type | DMI 3.0 + |
| chipset | Lewisburg + |
| clock multiplier | 23 + |
| core count | 16 + |
| core family | 6 + |
| core name | Cascade Lake SP + |
| core stepping | L1 + |
| cpuid | 0x50655 + |
| designer | Intel + |
| family | Xeon Gold + |
| first announced | April 2, 2019 + |
| first launched | April 2, 2019 + |
| full page name | intel/xeon gold/5218n + |
| has locked clock multiplier | true + |
| instance of | microprocessor + |
| isa | x86-64 + |
| isa family | x86 + |
| l1$ size | 1,024 KiB (1,048,576 B, 1 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 512 KiB (524,288 B, 0.5 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 512 KiB (524,288 B, 0.5 MiB) + |
| l2$ description | 16-way set associative + |
| l2$ size | 16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) + |
| l3$ description | 11-way set associative + |
| l3$ size | 22 MiB (22,528 KiB, 23,068,672 B, 0.0215 GiB) + |
| ldate | April 2, 2019 + |
| main image | |
| manufacturer | Intel + |
| market segment | Server + |
| max cpu count | 4 + |
| max memory | 1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) + |
| microarchitecture | Cascade Lake + |
| model number | 5218N + |
| name | Xeon Gold 5218N + |
| package | FCLGA-3647 + |
| part number | CD8069504289900 + |
| platform | Purley + |
| process | 14 nm (0.014 μm, 1.4e-5 mm) + |
| release price | $ 1,375.00 (€ 1,237.50, £ 1,113.75, ¥ 142,078.75) + |
| release price (tray) | $ 1,375.00 (€ 1,237.50, £ 1,113.75, ¥ 142,078.75) + |
| s-spec | SRFD9 + |
| series | 5200 + |
| smp max ways | 4 + |
| socket | Socket P + and LGA-3647 + |
| tdp | 105 W (105,000 mW, 0.141 hp, 0.105 kW) + |
| technology | CMOS + |
| thread count | 32 + |
| word size | 64 bit (8 octets, 16 nibbles) + |