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Lake Crest - Microarchitectures - Intel Nervana
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Lake Crest µarch
General Info
Arch TypeNPU
DesignerNervana
ManufacturerTSMC
Process28 nm
Succession

Lake Crest is a neural processor microarchitecture designed by Nervana.

Process Technology

Lake Crest is fabricated on TSMC's 28 nm process.

Architecture

  • Tensor-based architecture
    • Nervana Engine
  • Flexpoint number format
  • HBM2 memory

This list is incomplete; you can help by expanding it.

Block Diagram

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Memory Hierarchy

  • 32 GiB on-package HBM2
    • 1 TiB/s
codenameLake Crest +
designerNervana +
full page namenervana/microarchitectures/lake crest +
instance ofmicroarchitecture +
manufacturerTSMC +
nameLake Crest +
process28 nm (0.028 μm, 2.8e-5 mm) +