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From WikiChip
SHAVE v3.0 (Fragrak) - Microarchitectures - Intel Movidius
< movidius
Edit Values | |
SHAVE v3.0 µarch | |
General Info | |
Arch Type | Accelerator |
Designer | Movidius |
Manufacturer | TSMC |
Introduction | 2014 |
Process | 28 nm |
Pipeline | |
Type | VLLIW |
Instructions | |
ISA | SHAVE, SPARC v8 |
Cache | |
L2 Cache | 256 KiB/chip 2-way set associative |
Side Cache | 128-256 MiB SDRAM/chip |
Succession | |
Fragrak or Streaming Hybrid Architecture Vector Engine v3.0 (SHAVE v3.0) is an accelerator microarchitecture designed by Movidius for their vision processors, serving as a successor to the SHAVE v2.0. SHAVE-based products are branded as the Myriad 2 family of vision processors.
Retrieved from "https://en.wikichip.org/w/index.php?title=movidius/microarchitectures/shave_v3.0&oldid=75207"
codename | SHAVE v3.0 + |
designer | Movidius + |
first launched | 2014 + |
full page name | movidius/microarchitectures/shave v3.0 + |
instance of | microarchitecture + |
instruction set architecture | SHAVE + and SPARC v8 + |
manufacturer | TSMC + |
name | SHAVE v3.0 + |
process | 28 nm (0.028 μm, 2.8e-5 mm) + |