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SHAVE v2.0 µarch
General Info
Arch Type	Accelerator
Designer	Movidius
Manufacturer	TSMC
Introduction	2011
Pipeline
Type	VLIW

Streaming Hybrid Architecture Vector Engine v2.0 (SHAVE v2.0) is an accelerator microarchitecture designed by Movidius for their vision processors. SHAVE-based products are branded as the Myriad family of vision processors.

History

The original SHAVE architecture was designed primarily for the acceleration of game physics. Low demand for expensive physics acceleration in smartphones has forced to re-focused on image and vision processing. Their architecture was versatile enough that it allowed for fairly simple modification to target machine vision processing.

Process Technology

Main article: 65 nm lithography process

This microarchitecture was designed for TSMC's 65 nm process.

Architecture

• Hybrid RISC-DSP-GPU VLIW architecture
• 20 GFLOPS computational power
  • 180 MHz
  • At 300 mW
• Predicated execution
• Branch delay slots
• Tailored to streaming workloads
• 128-bit vector arithmetic
  • 8/16/32-bit integer
  • 16/32-bit floating point
• Full support for sparse data structures (matrix/array, random access)

Instruction Set

SHAVE supports a mixture of many different types of instructions belonging to a number of different classes of architectures.

• RISC style
  • Instruction predication
  • Large set of integer operations
• VLIW style
  • Parallel functional units controlled by VLIW instructions
  • 8/16/32-bit x 1-4 SIMD int
• DSP style
  • Zero overhead looping
  • Modulo addressing
  • Transparent DMA modes
  • FFT, Viterbi, etc..
  • Parallel comparisons
• GPU style
  • Streaming operations
  • 16/32-bit FP operations
  • Texture management unit

Block Diagram

Entire SoC

Individual Core

Overview

Architecturally, SHAVE is organized similar to IBM's CELL architecture. There are independent SHAVE cores, with up to eight in this generation may be chained together. Cores benefit from zero penalty from their two neighbors closest, an intrinsic property of architecture that inherently benefits most code. The chip features an L2 cache that is shared by all the cores as well as an integrated DDR2 memory controller that is connected to an on-package KGD stacked die ranging from 8 to 64 MiB of SDRAM. A large set of peripherals are attached to the parameter of the chip which communicate with the cores via the AXI bus. Those peripherals include support for two high-resolution cameras (up to 12 megapixel) at high rate and high-resolution LCD controllers. The various peripherals can be software-multiplexed via the limited number of I/O pins in the package. The overall management controller core is a synthesizable SPARC V8 LEON3.

Performance claims

Movidius reported very high performance numbers for their chip. Fabricated on a 65 nm process and operating at 180 MHz and consuming 300 milliwatt, the full chip is capable of doing 300 GOPS or just over 1 TOPS per watt for 8-bit arithmetic for their integer arithmetic operations and 60 GOPS for 8-bit vector operations.

Package

Movidius packaged those chips in an 8x8 mm BGA package with 225 balls. The die is then bumpped on top of a custom FR-4 substrate. The SDRAM is then wire bond on top of the Myriad die.

Floorplan

The full chip consists of just two macros - the CMX block and the SHAVE core block. The whole die was place and routed with those two marcros with the rest routed flat at the end.

Myriad Die

• TSMC's 65 nm process
• < 64 mm² die size