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From WikiChip
SABRE - Intel Movidius
< movidius
| Edit Values | |
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| General Info | |
| Microarchitecture |
SABRE was a test microprocessor designed by Movidius for the acceleration of machine vision. The SABRE microprocessor eventually lead to the production definition of the Myriad 1 line of vision accelerators. SABRE is capable of 20 GLOPS at low 100s mW of power through the use of 9 execution units consisting of a SPARC V8 LEON3 core and 8 additional SHAVE v2.0 cores.
The test platform consisted of a Samsung 6410 daughtercard which incoluded an S3C6410X processor (ARM11) and a Movidius MV0108 SABRE daughtercard which had the SABRE processor.
Retrieved from "https://en.wikichip.org/w/index.php?title=movidius/sabre&oldid=75077"
Facts about "SABRE - Intel Movidius"
| base frequency | 180 MHz (0.18 GHz, 180,000 kHz) + |
| core count | 9 + |
| designer | Movidius + |
| full page name | movidius/sabre + |
| instance of | microprocessor + |
| isa | SPARC V8 + and SHAVE + |
| isa family | SPARC + and SHAVE + |
| ldate | 1900 + |
| manufacturer | TSMC + |
| market segment | Embedded + and Mobile + |
| microarchitecture | LEON3 + and SHAVE v2.0 + |
| model number | SABRE + |
| name | SABRE + |
| process | 65 nm (0.065 μm, 6.5e-5 mm) + |
| technology | CMOS + |
| thread count | 9 + |
| word size | 32 bit (4 octets, 8 nibbles) + |