From WikiChip
KaiXian (ZX/KX) - Zhaoxin
< zhaoxin
Revision as of 00:32, 15 January 2018 by ChipIt (talk | contribs) (Created page with "{{zhaoxin title|KaiXian (ZX/KX)}} {{ic family | title = KaiXian | image = | caption = | no image = Yes | developer = Zhaox...")
(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)

KaiXian
Developer Zhaoxin, VIA Technologies
Manufacturer TSMC, HLMC
Type Microprocessors
Introduction 2016 (announced)
2016 (launch)
ISA x86
µarch Isaiah, Zhangjiang, WuDaoKou, LuJiaZui
Word size 64 bit
8 octets
16 nibbles
Process 40 nm
0.04 μm
4.0e-5 mm
, 28 nm
0.028 μm
2.8e-5 mm
Technology CMOS
Succession
←
QuadCore

Zhaoxin KaiXian (ZX/KX) is a family of x86 microprocessors developed by Zhaoxin for the Chinese market.

Retrieved from "https://en.wikichip.org/w/index.php?title=zhaoxin/kaixian&oldid=72567"
Facts about "KaiXian (ZX/KX) - Zhaoxin"
RDF feed
designerZhaoxin + and VIA Technologies +
first announced2016 +
first launched2016 +
full page namezhaoxin/kaixian +
instance ofmicroprocessor family +
instruction set architecturex86 +
main designerZhaoxin +
manufacturerTSMC + and HLMC +
microarchitectureIsaiah +, Zhangjiang +, WuDaoKou + and LuJiaZui +
nameKaiXian +
process40 nm (0.04 μm, 4.0e-5 mm) + and 28 nm (0.028 μm, 2.8e-5 mm) +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +