Semiconductor & Computer Engineering
-
WikiChip
WikiChip
-
Architectures
Popular x86
-
Intel
- Client
- Server
- Big Cores
- Small Cores
-
AMD
Popular ARM
-
ARM
- Server
- Big
- Little
-
Cavium
-
Samsung
-
-
Chips
Popular Families
-
Ampere
-
Apple
-
Cavium
-
HiSilicon
-
MediaTek
-
NXP
-
Qualcomm
-
Renesas
-
Samsung
-
From WikiChip
ZhangJiang - Microarchitectures - Zhaoxin
< zhaoxin
| Edit Values | |
| WuDaoKou µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Zhaoxin |
| Manufacturer | TSMC |
| Introduction | 2015 |
| Process | 28 nm |
| Core Configs | 2, 4, 8 |
| Pipeline | |
| Type | Superscalar |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Instructions | |
| ISA | x86-64 |
| Succession | |
ZhangJiang is the successor to Isaiah II, a 28 nm x86 microarchitecture designed by Zhaoxin for mainstream laptops, desktops, and servers.
Retrieved from "https://en.wikichip.org/w/index.php?title=zhaoxin/microarchitectures/zhangjiang&oldid=72434"
Facts about "ZhangJiang - Microarchitectures - Zhaoxin"
| codename | WuDaoKou + |
| core count | 2 +, 4 + and 8 + |
| designer | Zhaoxin + |
| first launched | 2015 + |
| full page name | zhaoxin/microarchitectures/zhangjiang + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | WuDaoKou + |
| process | 28 nm (0.028 μm, 2.8e-5 mm) + |