Semiconductor & Computer Engineering
From WikiChip
Drive Xavier - Nvidia
| Edit Values | |
| Drive Xavier | |
| General Info | |
| Designer | Nvidia |
| Manufacturer | TSMC |
| Market | Artificial Intelligence |
| Introduction | January 8, 2018 (announced) |
| General Specs | |
| Series | Drive |
| Microarchitecture | |
| ISA | ARMv8 (ARM) |
| Process | 12 nm |
| Transistors | 9,000,000,000 |
| Technology | CMOS |
| Die | 350 mm² |
| Word Size | 64 bit |
| Cores | 8 |
| Threads | 8 |
| Electrical | |
| TDP | 30 W |
| TDP (Typical) | 20 W |
Drive Xavier is a 64-bit ARM high-performance autonomous machine SoC designed by NVIDIA and introduced in 2018.
Overview
The Drive Xavier is an autonomous machine system on chip designed by NVIDIA and introduced at CES 2018. Silicon came back in the last week of December 2017 with sampling started in the first quarter of 2018. NVIDIA plans on mass production by the end of the year. NVIDIA reported that the product is a result of $2 billion R&D and 8,000 engineering hours.
Die
Facts about "Tegra Xavier - Nvidia"
| core count | 8 + |
| designer | Nvidia + |
| die area | 350 mm² (0.543 in², 3.5 cm², 350,000,000 µm²) + |
| first announced | January 8, 2018 + |
| full page name | nvidia/tegra/xavier + |
| has ecc memory support | true + |
| instance of | microprocessor + |
| isa | ARMv8 + |
| isa family | ARM + |
| ldate | 3000 + |
| manufacturer | TSMC + |
| market segment | Artificial Intelligence + |
| max memory bandwidth | 127.1 GiB/s (130,150.4 MiB/s, 136.473 GB/s, 136,472.586 MB/s, 0.124 TiB/s, 0.136 TB/s) + |
| max memory channels | 8 + |
| name | Drive Xavier + |
| process | 12 nm (0.012 μm, 1.2e-5 mm) + |
| series | Drive + |
| supported memory type | LPDDR4-2133 + |
| tdp | 30 W (30,000 mW, 0.0402 hp, 0.03 kW) + |
| tdp (typical) | 20 W (20,000 mW, 0.0268 hp, 0.02 kW) + |
| technology | CMOS + |
| thread count | 8 + |
| transistor count | 9,000,000,000 + |
| word size | 64 bit (8 octets, 16 nibbles) + |