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From WikiChip
Goldmont Plus - Microarchitectures - Intel
< intel | microarchitectures
Edit Values | |
Goldmont µarch | |
General Info | |
Arch Type | CPU |
Designer | Intel |
Manufacturer | Intel |
Introduction | August 30, 2016 |
Process | 14 nm |
Core Configs | 2, 4, 8 |
Pipeline | |
Type | Superscalar |
Speculative | Yes |
Reg Renaming | Yes |
Stages | 12-14 |
Instructions | |
ISA | IA-32, x86-64 |
Extensions | MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, SHA |
Cache | |
L1I Cache | 32 KiB/Core 8-way set associative |
L1D Cache | 24 KiB/Core 6-way set associative |
L2 Cache | 1 MiB/2 Cores 16-way set associative |
Cores | |
Core Names | Apollo Lake |
Succession | |
Goldmont Plus |
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/goldmont_plus&oldid=56342"
Facts about "Goldmont Plus - Microarchitectures - Intel"
codename | Goldmont + |
core count | 2 +, 4 + and 8 + |
designer | Intel + |
first launched | August 30, 2016 + |
full page name | intel/microarchitectures/goldmont plus + |
instance of | microarchitecture + |
instruction set architecture | IA-32 + and x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Goldmont + |
pipeline stages (max) | 14 + |
pipeline stages (min) | 12 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |