Semiconductor & Computer Engineering
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Celerity - Microarchitectures
| Edit Values | |
| Celerity µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | University of Michigan, University of Washington, Cornell University, University of California |
| Manufacturer | TSMC |
| Process | 16 nm |
| Instructions | |
| ISA | RISC-V |
| Extensions | Integer, Multiply |
Celerity is a custom RISC-V-based neural processor microarchitecture. The work is a joint effort by the Bespoke Silicon Group at the University of Washington, Cornell University, University of Michigan, and UC San Diego.
Contents
Process technology
Celerity is fabricated on TSMC 16 nm process.
Overview
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Compute tiers
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General-purpose tier
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Massively parallel tier
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Specialization tier
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Die
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Bibliography
- 2019 Symposia on VLSI Technology and Circuits (VLSI 2019).
- IEEE Hot Chips 29 Symposium (HCS) 2017.
Categories:
- cpu microarchitectures by university of michigan
- microarchitectures by university of michigan
- microarchitectures by university of washington
- cpu microarchitectures by university of washington
- microarchitectures by cornell university
- cpu microarchitectures by cornell university
- microarchitectures by university of california
- cpu microarchitectures by university of california
- all microarchitectures
Facts about "Celerity - Microarchitectures"
| codename | Celerity + |
| designer | University of Michigan +, University of Washington +, Cornell University + and University of California + |
| full page name | umich/microarchitectures/celerity + |
| instance of | microarchitecture + |
| instruction set architecture | RISC-V + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Celerity + |
| process | 16 nm (0.016 μm, 1.6e-5 mm) + |