Semiconductor & Computer Engineering
| Edit Values | |
| Xeon Platinum 8260L | |
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| General Info | |
| Designer | Intel |
| Manufacturer | Intel |
| Model Number | 8260L |
| Part Number | CD8069504201001 |
| S-Spec | SRF9G |
| Market | Server |
| Introduction | April 2, 2019 (announced) April 2, 2019 (launched) |
| Release Price | $12,599.00 (tray) |
| Shop | Amazon |
| General Specs | |
| Family | Xeon Platinum |
| Series | 8200 |
| Locked | Yes |
| Frequency | 2,400 MHz |
| Turbo Frequency | 3,900 MHz (1 core) |
| Clock multiplier | 24 |
| CPUID | 0x50655 |
| Microarchitecture | |
| ISA | x86-64 (x86) |
| Microarchitecture | Cascade Lake |
| Platform | Purley |
| Chipset | Lewisburg |
| Core Name | Cascade Lake SP |
| Core Family | 6 |
| Core Stepping | B1 |
| Process | 14 nm |
| Technology | CMOS |
| Word Size | 64 bit |
| Cores | 24 |
| Threads | 48 |
| Max Memory | 4.5 TiB |
| Multiprocessing | |
| Max SMP | 8-Way (Multiprocessor) |
| Electrical | |
| TDP | 165 W |
| Packaging | |
| Package | FCLGA-3647 (FCLGA) |
| Dimension | 76.16 mm × 56.6 mm |
| Pitch | 0.8585 mm × 0.9906 mm |
| Contacts | 3647 |
| Socket | Socket P, LGA-3647 |
Xeon Platinum 8260L is a 64-bit 24-core x86 high-performance server microprocessor introduced by Intel in early 2019. The Platinum 8260L is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 8-way multiprocessing, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor supports up 4.5 TiB of hexa-channel DDR4-2933 memory, operates at 2.4 GHz with a TDP of 165 W and features a turbo boost frequency of up to 3.9 GHz.
As indicated by the "L" suffix, this model features extended memory support of up to 4.5 TiB of memory.
Contents
Cache
- Main article: Cascade Lake § Cache
The Xeon Platinum 8260L features a larger non-default 35.75 MiB of L3, a size that would normally be found on a 26-core part.
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options |
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Features
[Edit/Modify Supported Features]
| full page name | intel/xeon platinum/8260l + |
| instance of | microprocessor + |
| ldate | 1900 + |