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SX-Aurora - Microarchitectures - NEC
| Edit Values | |
| SX-Aurora µarch | |
| General Info | |
| Arch Type | VPU |
| Designer | NEC |
| Manufacturer | TSMC |
| Introduction | 2018 |
| Core Configs | 8 |
| Pipeline | |
| Type | Superscalar, Pipelined |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Stages | 8 |
| Decode | 4-way |
| Cache | |
| L1I Cache | 32 KiB/core |
| L1D Cache | 32 KiB/core |
| L2 Cache | 256 KiB/core |
| L3 Cache | 16 MiB/chip |
| Succession | |
SX-Aurora is NEC's successor to the SX-ACE, a 16 nm microarchitecture for vector processors first introduced in 2018.
Contents
History
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Architecture
Key changes from SX-ACE
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Block Diagram
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Memory Hierarchy
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= Overview
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Vector engine (VE) card
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This section is empty; you can help add the missing info by editing this page. |
Die
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This section is empty; you can help add the missing info by editing this page. |
Bibliography
- Template:hcbib
- Supercomputing 2018, NEC Aurora Forum
- Some information was obtained directly from NEC
Facts about "SX-Aurora - Microarchitectures - NEC"
| codename | SX-Aurora + |
| core count | 8 + |
| designer | NEC + |
| first launched | 2018 + |
| full page name | nec/microarchitectures/sx-aurora + |
| instance of | microarchitecture + |
| manufacturer | TSMC + |
| name | SX-Aurora + |
| pipeline stages | 8 + |