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This is the discussion page for the nec/microarchitectures/sx-aurora page.

256 physical vector registers?[edit]

Where does this information come from?

I've not seen such a claim anywhere else, and frankly it does not make a lot of sense to me. That would make the vector register a whopping 256×256×8bytes = 8MBytes.

More importantly, it would take 192 register renames to use each register at least once. It would need an extraordinarily large reorder buffer to make this happen.

And as there are still unused bits in the instruction format, much better use could be made of those registers by at least partially exposing that large register file to the user. In fact, what made me comment here is that I'd be angry at NEC's hardware engineers to not at least expose 128 architectural hardware registers if 256 physical registers existed.

Taking all that together, I suspect the 256 physical vector registers per Vector Processing Unit don't in fact exist. 15:45, 22 April 2020 (EDT)

I wanted to follow up on this. The information in the article was obtained directly from NEC during our briefing with them so it's entirely possible we have info no one else does. NEC told us that the SX-Aurora features 256 physical vector registers on which the 64 architectural registers are renamed. I think your math is a bit wrong wrt 8 MiB. With 8-byte elements and 265 elements, a single register requires 2 KiB of storage. That's 128 KiB for 64 architectural registers and 512 KiB for the entire 256-vector physical register file. The actual partitioning is likely 128 KiB for architectural + 384 KiB for physical. --David (talk) 23:06, 13 May 2020 (EDT)

Cache bandwidth listed as 3GB/s[edit]

i believe there is a typo stating the LLC bandwidth as 3GB/s when it should be 3TB/s

That's correct. Thank you. --David (talk) 23:08, 13 May 2020 (EDT)