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M3-8114Y
General Info
Designer	Intel
Manufacturer	Intel
Model Number	M3-8114Y
Market	Mobile
Shop	Amazon
General Specs
Family	Core M3
Series	M3-8000
Locked	Yes
Frequency	1,500 MHz
Turbo Frequency	2,600 MHz (1 core)
Bus type	OPI
Bus rate	4 GT/s
Clock multiplier	15
Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Cannon Lake
Chipset	Cannon Point
Core Name	Cannon Lake Y
Core Family	6
Core Model	102
Process	10 nm
Technology	CMOS
Word Size	64 bit
Cores	2
Threads	4
Max Memory	16 GiB
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Electrical
TDP	5.2 W

Core M3-8114Y is a 64-bit dual-core low-end performance ultra-low power x86 mobile microprocessor introduced by Intel in early 2018. This chip, which is based on the Cannon Lake microarchitecture, is fabricated on Intel's 10 nm process. The M3-8114Y operates at 1.5 GHz with a TDP of 5.2 W supporting a Turbo Boost frequency of 2.6 GHz. The processor supports up to 16 GiB of dual-channel LPDDR4X-2133 memory and incorporates Intel's UHD Graphics 715? IGP operating at ? MHz with a burst frequency of ? MHz.

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Cannon Lake § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 128 KiB 131,072 B 0.125 MiB L1I$ 64 KiB 65,536 B 0.0625 MiB 2x32 KiB 8-way set associative   L1D$ 64 KiB 65,536 B 0.0625 MiB 2x32 KiB 8-way set associative write-back L2$ 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB     2x256 KiB 4-way set associative write-back L3$ 4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB     2x2 MiB 16-way set associative write-back

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type LPDDR4-2133, LPDDR4X-2133 Supports ECC No Max Mem 16 GiB Controllers 1 Channels 2 Max Bandwidth 31.78 GiB/s 32,542.72 MiB/s 34.124 GB/s 34,123.515 MB/s 0.031 TiB/s 0.0341 TB/s Bandwidth Single 15.89 GiB/s Double 31.78 GiB/s

Expansions

[Edit/Modify Expansions Info]

	Expansion Options
	PCIe Revision 3.0 Max Lanes 10 Configs 1x4, 2x2, 1x2+2x1, 4x1

Graphics

[Edit/Modify IGP Info]

Integrated Graphics Information

GPU UHD Graphics 715 Designer Intel Execution Units 40? "?" can not be assigned to a declared number type with value 40. Max Displays 3 Max Memory 16 GiB 16,384 MiB 16,777,216 KiB 17,179,869,184 B Frequency 300? MHz "?MHz" is not declared as a valid unit of measurement for this property. Burst Frequency ? MHz "? MHz" is not a number. Output DP, eDP, HDMI, DVI Max Resolution HDMI 4096x2304 @60 Hz DP 4096x2304 @60 Hz eDP 4096x2304 @60 Hz Standards DirectX 12 OpenGL 4.5 OpenCL 2.0 DP 1.2 eDP 1.4 HDMI 2.0 Additional Features Intel Quick Sync Video Intel InTru 3D Intel Clear Video Intel Clear Video HD

Features

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX MMX Extension EMMX Extended MMX Extension SSE Streaming SIMD Extensions SSE2 Streaming SIMD Extensions 2 SSE3 Streaming SIMD Extensions 3 SSSE3 Supplemental SSE3 SSE4.1 Streaming SIMD Extensions 4.1 SSE4.2 Streaming SIMD Extensions 4.2 SSE4a Streaming SIMD Extensions 4a AVX Advanced Vector Extensions AVX2 Advanced Vector Extensions 2 AVX-512 Advanced Vector 512-bit AVX512F AVX-512 Foundation AVX512CD AVX-512 Conflict Detection AVX512BW AVX-512 Byte and Word AVX512DQ AVX-512 Doubleword and Quadword Instructions AVX512VL AVX-512 Vector Length AVX512_IFMA AVX-512 Integer Fused Multiply-Add AVX512_VBMI AVX-512 Vector Bit Manipulation Instructions ABM Advanced Bit Manipulation BMI1 Bit Manipulation Instruction Set 1 BMI2 Bit Manipulation Instruction Set 2 FMA3 3-Operand Fused-Multiply-Add AES AES Encryption Instructions RdRand Hardware RNG SHA SHA Extensions ADX Multi-Precision Add-Carry CLMUL Carry-less Multiplication Extension F16C 16-bit Floating Point Conversion x86-16 16-bit x86 x86-32 32-bit x86 x86-64 64-bit x86 Real Real Mode Protected Protected Mode SMM System Management Mode FPU Integrated x87 FPU NX No-eXecute HT Hyper-Threading TBT 2.0 Turbo Boost Technology 2.0 EIST Enhanced SpeedStep Technology SST Speed Shift Technology VT-x VT-x (Virtualization) VT-d VT-d (I/O MMU virtualization) EPT Extended Page Tables (SLAT) MPX Memory Protection Extensions SGX Software Guard Extensions Secure Key Secure Key Technology SMEP OS Guard Technology Flex Memory Flex Memory Access ISRT Smart Response Technology MWT My WiFi Technology