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EPYC Embedded 3451
General Info
Designer	AMD
Manufacturer	GlobalFoundries
Model Number	3451
Market	Server, Embedded
Introduction	February 21, 2018 (announced) February 21, 2018 (launched)
Release Price	$880
Shop	Amazon
General Specs
Family	EPYC Embedded
Series	3000
Frequency	2,150 MHz
Turbo Frequency	3,000 MHz (1 core)
Clock multiplier	21.5
Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Zen
Core Name	Snowy Owl
Process	14 nm
Transistors	9,600,000,000
Technology	CMOS
Die	213 mm²
MCP	Yes (2 dies)
Word Size	64 bit
Cores	16
Threads	32
Max Memory	1 TiB
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Electrical
TDP	100 W
Tjunction	0 °C – 95 °C
Packaging
Template:packages/amd/package sp4

EPYC Embedded 3451 is a 64-bit hexadeca-core x86 embedded microprocessor introduced by AMD in early 2018 for dense servers and edge devices. Fabricated on a 14 nm process based on the Zen microarchitecture, this chip operates at 2.15 GHz with a TDP of 100 W and a turbo frequency of up to 3 GHz. The 3451 supports up to 1 TiB of quad-channel DDR4-2666 ECC memory.

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Zen § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 1.5 MiB 1,536 KiB 1,572,864 B L1I$ 1 MiB 1,024 KiB 1,048,576 B 16x64 KiB 4-way set associative   L1D$ 512 KiB 524,288 B 0.5 MiB 16x32 KiB 8-way set associative write-back L2$ 8 MiB 8,192 KiB 8,388,608 B 0.00781 GiB     16x512 KiB 8-way set associative write-back L3$ 32 MiB 32,768 KiB 33,554,432 B 0.0313 GiB     4x8 MiB 16-way set associative write-back

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR4-2666 Supports ECC Yes Max Mem 1 TiB Controllers 4 Channels 4 Max Bandwidth 79.47 GiB/s 81,377.28 MiB/s 85.33 GB/s 85,330.263 MB/s 0.0776 TiB/s 0.0853 TB/s Bandwidth Single 19.87 GiB/s Double 39.74 GiB/s Quad 79.47 GiB/s

[Edit] Official AMD Supported Memory Configurations
Quad Channel	Single Rank	1 DIMM per channel	4 of 8	DDR4-2666
		2 DIMMs per channel	8 of 8	DDR4-2133
	Dual Rank	1 DIMM per channel	4 of 8	DDR4-2400
		2 DIMMs per channel	8 of 8	DDR4-1866

Expansions

The EPYC Embedded 3451 has 64 PCIe lanes that are MUX'ed with a number of other ports and can be reconfigured as either SATA ports (up to 16 such ports), or as GbE ports (up to 10 such ports), or any mixed configuration of those options.

[Edit/Modify Expansions Info]

	Expansion Options
PCIe Revision: 3.0 Max Lanes: 64 Configuration: x16, x8, x4, x2