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General Info
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Skylake (SKL) is Intel's successor to Broadwell, a 14 nm process microarchitecture for mainstream desktops, servers, and mobile devices. Skylake succeeded the short-lived Broadwell which experienced severe delays. Skylake is the "Architecture" phase as part of Intel's PAO model. The microarchitecture was developed by Intel's R&D center in Haifa, Israel.

For desktop and mobile, Skylake is branded as 6th Generation Intel Core i3, Core i5. and Core i7 processors. For server class processors, Intel branded it as Xeon E3 v5, Xeon E5 v5, and Xeon E7 v5.

Codenames

Core Abbrev Target
Skylake Y SKL-Y 2-in-1s detachable, tablets, and computer sticks
Skylake U SKL-U Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room
Skylake H SKL-H Ultimate mobile performance, mobile workstations
Skylake S SKL-S Desktop performance to value, AiOs, and minis
Skylake X SKL-X High-end desktops & enthusiasts market
Skylake W SKL-W Workstations

Process Technology

Main article: Broadwell § Process Technology

Skylake uses the same 14 nm process used for the Broadwell microarchitecture.

Architecture

Overall Skylake builds upon Intel's previous microarchitecture, Broadwell, but includes a more beefed up front end, more optimized execution engine, and numerous number of smaller enhancements. Intel designed Skylake to encompass a wide range of devices and applications with a large emphasis on mobile with models ranging from as low as 4.5 W to as high as 100 W.

Key changes from Broadwell

  • 8x performance/watt over Nehalem (Up from 3.5x in Haswell)
  • Bus/Interface to Chipset
    • DMI 3.0 (from 2.0)
      • Skylake S and Skylake H cores, connected by 4-lane DMI 3.0
      • Skylake Y and Skylake U cores have chipset in the same package (simplified OPIO)
      • Increase in transfer rate from 5.0 GT/s to 8.0 GT/s (~3.93GB/s up from 2GB/s) per lane
      • Limits motherboard trace design to 7 inches max from (down from 8) from the CPU to chipset
  • Front End
    • Larger legacy pipeline delivery (5 µOPs, up from 4)
    • Larger IDQ delivery (6 µOPs, up from 4)
    • 2.28x larger allocation queue (64/thread, up from 28/thread)
    • Improved branch prediction unit
  • Execution Engine
    • Larger re-order buffer (224 entries, up from 192)
    • Larger scheduler (97 entries, up from 64)
      • Larger Integer Register File (180 entries, up from 160)
    • Larger store buffer (56 entries, up from 42)
  • Memory
    • Support for faster DDR-2400 memory
    • L2$ was changed from 8-way to 4-way set associative
    • L3$ re-gained 512 KiB/core (See §eDRAM architectural changes for the reason)
    • A new coherent cache fabric implementation
      • doubles the throughput of the last level cache (LLC, L3$ in this case) miss handling
      • 50% improvement in bandwidth/watt
      • new eDRAM cache architecture for higher bandwidth
  • TLBs
    • ITLB
      • 4 KiB page translations was changed from 4-way to 8-way associative
    • STLB
      • 4 KiB + 2 MiB page translations was changed from 6-way to 12-way associative
  • Electrical
    • The fully integrated voltage regulator (FIVR) is moved back to the motherboard
      • Originally intended to be a cost-cutting measure by moving the FIVR on-die as well as making it more efficient, the move resulted in unintentionally making the FIVR the limiting factor when it came to overclocking.
  • Testability
    • New support for Direct Connect Interface (DCI), a new debugging transport protocol designed to allow debugging of closed cases (e.g. laptops, embedded) by accessing things such as JTAG through any USB 3 port.

CPU changes

  • Most ALU operations have 4 op/cycle 1 for 8 and 32-bit registers. 64-bit ops are still limited to 3 op/cycle. (16-bit throughput varies per op, can be 4, 3.5 or 2 op/cycle).
  • MOVSX and MOVZX have 4 op/cycle throughput for 16->32 and 32->64 forms, in addition to Haswell's 8->32, 8->64 and 16->64 bit forms.
  • ADC and SBB have throughput of 1 op/cycle, same as Haswell.
  • Vector moves have throughput of 4 op/cycle (move elimination).
  • Not only zeroing vector vpXORxx and vpSUBxx ops, but also vPCMPxxx on the same register, have throughput of 4 op/cycle.
  • Vector ALU ops are often "standardized" to latency of 4. for example, vADDPS and vMULPS used to have L of 3 and 5, now both are 4.
  • Fused multiply-add ops have latency of 4 and throughput of 0.5 op/cycle.
  • Throughput of vADDps, vSUBps, vCMPps, vMAXps, their scalar and double analogs is increased to 2 op/cycle.
  • Throughput of vPSLxx and vPSRxx with immediate (i.e. fixed vector shifts) is increased to 2 op/cycle.
  • Throughput of vANDps, vANDNps, vORps, vXORps, their scalar and double analogs, vPADDx, vPSUBx is increased to 3 op/cycle.
  • vDIVPD, vSQRTPD have approximately twice as good throughput: from 8 to 4 and from 28 to 12 cycles/op.
  • Throughput of some MMX ALU ops (such as PAND mm1, mm2) is decreased to 2 or 1 op/cycle (users are expected to use wider SSE/AVX registers instead).
New GPU Features & Changes
  • Adaptive scalable texture compression (ASTC)
  • 16x multi-sample anti-aliasing (MSAA)
  • Post depth test coverage mask
  • Floating point atomics (min/max/cmpexch)
  • Min/max texture filtering
  • Multi-plane overlays

eDRAM architectural changes

In Broadwell, the eDRAM was statically attached to the LLC (last level cache, L3$), effectively stealing half a Mebibyte per core in the process, but behaving as an architectural true level 4 cache. This was fundamentally changed in Skylake. In Skylake, Intel removed the eDRAM from the LLC to its own array, re-freeing the 512 KiB (hence the 1.5 MiB/core in Broadwell and 2 MiB back in Skylake), but also removing the undesired dependency between the capacity of the eDRAM and the number of cores. Skylake's cache is effectively no longer a true level 4 cache but rather a memory side cache. This has a number of benefits such as that each and every memory access that goes through the memory controller gets looked up in the eDRAM. On a satisfied hit, the value is obtained from there. On a miss, a value gets allocated and stored in the eDRAM (subject to a number of restrictions, for example no I/O devices requests get cached on the eDRAM).

Skylake vs Broadwell eDRAM Architecture
Broadwell Skylake
broadwell edram setup.svg skylake edram setup.svg

The new eDRAM changes mean it's no longer architectural - capable of caching any data (including "unreachable memory", display engines, effectively any memory transfer not bound by software restrictions) and is entirely invisible to software (one exception noted later) in terms of coherency (note that no flushing is thus necessary to maintain coherency), ordering, or other organizational details. For optimal graphics performance, the graphics driver may decide to limit certain memory accesses to only the eDRAM, only the LLC, or in both of them.

Graphics

  • Improved underlying implementation of the memory QoS for higher resolution displays and the integrated image signal processor (ISP)
    • Allow for higher concurrent bandwidth
  • Skylake retires VGA support, multi-monitor support for up to 3 displays via HDMI 1.4, DP 1.2, and eDP 1.3 interfaces.
  • Direct X 12
  • OpenCL 2.0
  • OpenGL 4.4
  • Up to 24 EUs GT2 (same as Haswell); 48 EUs for GT3, and up to 72 EUs on Iris Pro Graphics
    • 1,152 GFLOPS
IGP Execution Units GT eDRAM Series (Y/U/H/S)
HD Graphics 12 2+1 - Y
HD Graphics 510 12 2+2 - U/S
HD Graphics 515 24 2+2 - Y
HD Graphics 520 24 4+2
2+2 		- U
HD Graphics 530 24 4+2
2+2 		- H/S
HD Graphics P530 24 4+2 - H
Iris Graphics 540 48 2+3e 64 MiB U
Iris Graphics 550 48 2+3e 64 MiB U
Iris Pro Graphics 580 72 4+4e 128 MiB H

New instructions

Main article: See §Added instructions for the complete list

Skylake introduced a number of new instructions:

  • SGX - Software Guard Extensions
  • MPX -Memory Protection Extensions
  • AVX-512 - Advanced Vector Extensions 512 (Only on high-end Xeon models (SKX))

"Speed Shift" (new power management)

Ever since the introduction of the modern power management unit on a microprocessor, it was effectively the role of the operating system to determine the desired operating frequency and voltage (i.e. a p-state) for the current workload. When the CPU utilization peaked, it was the role of the operating system to bump up the frequency to help cope with it. The issue has always been the limitation of the operating system. One such major limitation is the granularity of the operating system response time - usually in the 10s of milliseconds (anything lower than that would likely be too intensive and would not yield better result). A second major issue is that the operating system doesn't have an instantaneous observation of the microarchitectural behavior of the workload.

Intel introduced Speed Shift with Skylake, a new methodology for quickly alternating core frequencies in response to power loads. Intel introduced a new unit called Package Control Unit (PCU) which is effectively a full fledged microcontroller (containing power management logic and firmware) that collects and tracks many internal SoC statistics as well as external power telemetry (e.g. Psys and iMon). PCU is also capable of interfacing with the OS, BIOS, and DPTF. Speed Shift improves the performance of frequency shifting by off-loading the control from the operating system to the PCU.

Speed Shift effectively eliminates the need for the OS to manages the P-states - though it does have the final say (unless special exceptions occur such as thermal throttling). Intel calls this "autonomous P-state", allowing Speed Shift to kick in in a matter of just ~1 millisecond (whereas the operating system-based p-states control can be as slow as 30 ms). Speed Shift effectively reduces hitting peak frequency in around ~30 ms from over 100 ms (OS-based implementation as before). While Speed Shift is capable of full range shift by default, the operating system can set the minimum QoS, maximum frequency and power/performance hints when desired. The final result should be higher performance and specially higher responsiveness at power constrained form factors.

Power of System (Psys)

Psys (Power of System) is a way for the PCU to monitor the performance and the total platform power provided to the chip. The chip uses a number of autonomous algorithms (one for "Low Range" and one for "High Range"). The Low Range algorithm frequency is lowered to conserve energy. Algorithm is capable of overriding the low P state - a state calculated ever millisecond based on the active workload and system characteristics. The High Range algorithm deals with elevating frequency for the benefit of increase performance (at the cost of increase energy/inefficiency). The exact ratio of ΔPower/ΔPerformance ≤ αPreference can be finely controlled via the OS and user preferences.

Other Power Optimization

Skylake includes a number of additional power optimization changes:

  • AVX2 is now power gated - prior to Skylake, AVX2 was not power gated which meant it was susceptible to leakage. Starting with Skylake, those instruction are full power gated and turn off when not used.
  • Many older/legacy underused resources have been downscaled.
  • Various scenario-based power optimizations were done, including:
    • Idle power is reduced further
    • C1 state power reduction (improved dynamic capacitance Cdyn)

Overall Skylake enjoys better performance/Watt per core for 8x performance/watt over Nehalem.

Block Diagram

skylake block diagram.svg

Memory Hierarchy

Other than a few organizational changes (e.g. L2$ went from 8-way to 4-way set associative), the overall memory structure is identical to Broadwell/Haswell.

  • Cache
    • L1I Cache:
      • 32 KiB 8-way set associative
        • 64 B line size
        • shared by the two threads, per core
    • L1D Cache:
      • 32 KiB 8-way set associative
      • 64 B line size
      • shared by the two threads, per core
      • 4 cycles for fastest load-to-use
      • 64 Bytes/cycle load bandwidth
      • 32 Bytes/cycle store bandwidth
      • Write-back policy
    • L2 Cache:
      • unified, 256 KiB 4-way set associative
      • 12 cycles for fastest load-to-use
      • 64B/cycle bandwidth to L1$
      • Write-back policy
    • L3 Cache:
      • Up to 2 MiB
      • Per core
      • Up to 16-way set associative
      • Write-back policy
    • L4 Cache:
      • 128 MiB
      • Per package
      • Only on the Iris Pro GPUs

Skylake TLB consists of dedicated level one TLB for instruction cache and another one for data cache. Additionally there is a unified second level TLB.

  • TLBs:
    • ITLB
      • 4 KiB page translations:
        • 128 entries; 8-way set associative
        • dynamic partition; divided between the two threads
      • 2 MiB / 4 MiB page translations:
        • 8 entries; fully associative
        • Duplicated for each thread
    • DTLB
      • 4 KiB page translations:
        • 64 entries; 4-way set associative
        • fixed partition; divided between the two threads
      • 2 MiB / 4 MiB page translations:
        • 32 entries; 4-way set associative
        • fixed partition
      • 1G page translations:
        • 4 entries; 4-way set associative
        • fixed partition
    • STLB
      • 4 KiB + 2 MiB page translations:
        • 1536 entries; 12-way set associative
        • fixed partition
      • 1 GiB page translations:
        • 16 entries; 4-way set associative
        • fixed partition

Pipeline

Skylake, like its predecessor Broadwell, also has a dual-threaded and out-of-order pipeline.

Front-end

Skylake had its front-end bandwidth of µOPs deliver to the execution engine increase. The µOPs Cache now delivers 6 µOPs per clock (previously the cache only delivered 4 µOPs/clock), likewise the decoders now deliver 5 µOPs/clock (previously they were capable of only 4µOPs/clock). The branch predictor has also been improved. The branch predictor now has reduced penalty (i.e. lower latency) for wrong direct jump target prediction. Additionally, the instruction fetch unit is capable of looking much deeper into the stream of bytes. Finally, the allocation queue which interfaces between the front-end (in-order) and the execution engine (out-of-order) itself has been more than doubled to accommodate 64/thread (from 28/thread in Broadwell).

Execution engine

Like the front-end, the execution engine's ReOrder buffer has been increased to 224 entries (from 192 in Broadwell) in order to extract more instruction-level parallelism. Likewise the scheduler itself was increased considerably to 97 entries (from 64 in Broadwell). The integer register file was also slightly increased from 160 entries to 180.

The scheduler had its ports rearranged to better balance various instructions. For example, divide and sqrt instructions latency and throughput were improved. The latency and throughput of floating point ADD, MUL, and FMA were made uniformed at 4 cycles with a throughput of 2 ops/clock. Likewise the latency of AES instructions were significantly reduced from 7 cycles down to 4.

Dispatch Ports
Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7
ALU
Vec ALU 		ALU
Fast LEA
Vec ALU 		Load Addr
Store Addr 		Load Addr
Store Addr 		Store Data ALU
Fast LEA
Vec ALU 		ALU
Shift 		Store Addr
Vec Shift
Vec Add 		Vec Shift
Vec Add 		Vec Shuffle Branch
Vec Mul
FMA 		Vec Mul
FMA
DIV Slow Int
Branch2 Slow LEA

Execution Units

Execution Units
Execution Unit # of Units Instructions
ALU 4 add, and, cmp, or, test, xor, movzx, movsx, mov, (v)movdqu, (v)movdqa, (v)movap*, (v)movup*
DIV 1 divp*, divs*, vdiv*, sqrt*, vsqrt*, rcp*, vrcp*, rsqrt*, idiv
Shift 2 sal, shl, rol, adc, sarx, adcx, adox, etc...
Shuffle 1 (v)shufp*, vperm*, (v)pack*, (v)unpck*, (v)punpck*, (v)pshuf*, (v)pslldq, (v)alignr, (v)pmovzx*, vbroadcast*, (v)pslldq, (v)psrldq, (v)pblendw
Slow Int 1 mul, imul, bsr, rcl, shld, mulx, pdep, etc...
BM
Bit Manipulation
 		2 andn, bextr, blsi, blsmsk, bzhi, etc
FP Mov 1 (v)movsd/ss, (v)movd gpr
SMID Misc 1 STTNI, (v)pclmulqdq, (v)psadw, vector shift count in xmm
Vec ALU 3 (v)pand, (v)por, (v)pxor, (v)movq, (v)movq, (v)movap*, (v)movup*, (v)andp*, (v)orp*, (v)paddb/w/d/q, (v)blendv*, (v)blendp*, (v)pblendd
Vec Shift 2 (v)psllv*, (v)psrlv*, vector shift count in imm8
Vec Add 2 (v)addp*, (v)cmpp*, (v)max*, (v)min*, (v)padds*, (v)paddus*, (v)psign, (v)pabs, (v)pavgb, (v)pcmpeq*, (v)pmax, (v)cvtps2dq, (v)cvtdq2ps, (v)cvtsd2si, (v)cvtss2si
Vec Mul 2 (v)mul*, (v)pmul*, (v)pmadd*

Memory subsystem

Skylake has had its store buffer enlarged to 56 entries (up from 42 in Broadwell). Special care was taken to reduce the penalty for page-split loads: previously scenarios involving page-split loads were thought to be rarer than they actually are. This was addressed in Skylake with page-split loads are now made equal to other splits loads. Expect page split load penalty down to 5 cycles from 100 cycles in Broadwell. The average latency to forward a load to store has also been improved and stores that miss in the L1$ generate L2$ requests to the next level cache much earlier in Sklake than before.

The bandwidth from L2$ to L3$ has been improved and write bandwidth from L2$ to L3$ has also been increased from 4 cycles/line to 2 cycles/line.

Die

Quad-core Skylake die:

skylake (quad-core).png


skylake (quad-core) (annotated).png

Added instructions

SGX - Software Guard Extensions

MPX - Memory Protection Extensions

AVX-512 - Advanced Vector Extensions 512; These instructions can only be found on selected high-end Xeon models (codename SKX)

Cores

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All Skylake Chips

Skylake Chips
Main processorIGP
ModelµarchPlatformCoreLaunchedSDPTDPFreqMax MemNameFreqMax Freq
3855USkylakeSkylake U27 December 201515 W
15,000 mW
0.0201 hp
0.015 kW
1.6 GHz
1,600 MHz
1,600,000 kHz
32,768 MiB
33,554,432 KiB
34,359,738,368 B
32 GiB
0.0313 TiB
HD Graphics 510300 MHz
0.3 GHz
300,000 KHz
900 MHz
0.9 GHz
900,000 KHz
3955USkylakeSkylake U27 December 201515 W
15,000 mW
0.0201 hp
0.015 kW
2 GHz
2,000 MHz
2,000,000 kHz
32,768 MiB
33,554,432 KiB
34,359,738,368 B
32 GiB
0.0313 TiB
HD Graphics 510300 MHz
0.3 GHz
300,000 KHz
900 MHz
0.9 GHz
900,000 KHz
G3900SkylakeSkylake S19 October 201551 W
51,000 mW
0.0684 hp
0.051 kW
2.8 GHz
2,800 MHz
2,800,000 kHz
65,536 MiB
67,108,864 KiB
68,719,476,736 B
64 GiB
0.0625 TiB
HD Graphics 510350 MHz
0.35 GHz
350,000 KHz
950 MHz
0.95 GHz
950,000 KHz
G3900ESkylakeSkylake H2 January 201635 W
35,000 mW
0.0469 hp
0.035 kW
2.4 GHz
2,400 MHz
2,400,000 kHz
65,536 MiB
67,108,864 KiB
68,719,476,736 B
64 GiB
0.0625 TiB
HD Graphics 510350 MHz
0.35 GHz
350,000 KHz
950 MHz
0.95 GHz
950,000 KHz
G3900TSkylakeSkylake S19 October 201535 W
35,000 mW
0.0469 hp
0.035 kW
2.6 GHz
2,600 MHz
2,600,000 kHz
65,536 MiB
67,108,864 KiB
68,719,476,736 B
64 GiB
0.0625 TiB
HD Graphics 510350 MHz
0.35 GHz
350,000 KHz
950 MHz
0.95 GHz
950,000 KHz
G3900TESkylakeSkylake S19 October 201535 W
35,000 mW
0.0469 hp
0.035 kW
2.3 GHz
2,300 MHz
2,300,000 kHz
65,536 MiB
67,108,864 KiB
68,719,476,736 B
64 GiB
0.0625 TiB
HD Graphics 510350 MHz
0.35 GHz
350,000 KHz
950 MHz
0.95 GHz
950,000 KHz
G3902ESkylakeSkylake H2 January 201625 W
25,000 mW
0.0335 hp
0.025 kW
1.6 GHz
1,600 MHz
1,600,000 kHz
65,536 MiB
67,108,864 KiB
68,719,476,736 B
64 GiB
0.0625 TiB
HD Graphics 510350 MHz
0.35 GHz
350,000 KHz
950 MHz
0.95 GHz
950,000 KHz
G3920SkylakeSkylake S19 October 201551 W
51,000 mW
0.0684 hp
0.051 kW
2.9 GHz
2,900 MHz
2,900,000 kHz
65,536 MiB
67,108,864 KiB
68,719,476,736 B
64 GiB
0.0625 TiB
HD Graphics 510350 MHz
0.35 GHz
350,000 KHz
950 MHz
0.95 GHz
950,000 KHz
i3-6006USkylakeSkylake U10 November 201615 W
15,000 mW
0.0201 hp
0.015 kW
2 GHz
2,000 MHz
2,000,000 kHz
32,768 MiB
33,554,432 KiB
34,359,738,368 B
32 GiB
0.0313 TiB
HD Graphics 520300 MHz
0.3 GHz
300,000 KHz
900 MHz
0.9 GHz
900,000 KHz
i3-6098PSkylakeSkylake S27 December 201554 W
54,000 mW
0.0724 hp
0.054 kW
3.6 GHz
3,600 MHz
3,600,000 kHz
65,536 MiB
67,108,864 KiB
68,719,476,736 B
64 GiB
0.0625 TiB
HD Graphics 510350 MHz
0.35 GHz
350,000 KHz
1,050 MHz
1.05 GHz
1,050,000 KHz
i3-6100SkylakeSkylake S27 September 201551 W
51,000 mW
0.0684 hp
0.051 kW
3.7 GHz
3,700 MHz
3,700,000 kHz
65,536 MiB
67,108,864 KiB
68,719,476,736 B
64 GiB
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
1,050 MHz
1.05 GHz
1,050,000 KHz
i3-6100ESkylakeSkylake H12 October 201535 W
35,000 mW
0.0469 hp
0.035 kW
2.7 GHz
2,700 MHz
2,700,000 kHz
65,536 MiB
67,108,864 KiB
68,719,476,736 B
64 GiB
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
950 MHz
0.95 GHz
950,000 KHz
i3-6100HSkylakeSkylake H27 September 201535 W
35,000 mW
0.0469 hp
0.035 kW
2.7 GHz
2,700 MHz
2,700,000 kHz
65,536 MiB
67,108,864 KiB
68,719,476,736 B
64 GiB
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
900 MHz
0.9 GHz
900,000 KHz
i3-6100TSkylakeSkylake S27 September 201535 W
35,000 mW
0.0469 hp
0.035 kW
3.2 GHz
3,200 MHz
3,200,000 kHz
65,536 MiB
67,108,864 KiB
68,719,476,736 B
64 GiB
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
950 MHz
0.95 GHz
950,000 KHz
i3-6100TESkylakeSkylake S12 October 201535 W
35,000 mW
0.0469 hp
0.035 kW
2.7 GHz
2,700 MHz
2,700,000 kHz
65,536 MiB
67,108,864 KiB
68,719,476,736 B
64 GiB
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
1,000 MHz
1 GHz
1,000,000 KHz
i3-6100USkylakeSkylake U27 September 201515 W
15,000 mW
0.0201 hp
0.015 kW
2.3 GHz
2,300 MHz
2,300,000 kHz
32,768 MiB
33,554,432 KiB
34,359,738,368 B
32 GiB
0.0313 TiB
HD Graphics 520300 MHz
0.3 GHz
300,000 KHz
1,000 MHz
1 GHz
1,000,000 KHz
i3-6102ESkylakeSkylake H12 October 201525 W
25,000 mW
0.0335 hp
0.025 kW
1.9 GHz
1,900 MHz
1,900,000 kHz
65,536 MiB
67,108,864 KiB
68,719,476,736 B
64 GiB
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
950 MHz
0.95 GHz
950,000 KHz
i3-6120TSkylakeSkylake S35 W
35,000 mW
0.0469 hp
0.035 kW
65,536 MiB
67,108,864 KiB
68,719,476,736 B
64 GiB
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
950 MHz
0.95 GHz
950,000 KHz
i3-6157USkylakeSkylake UJune 201628 W
28,000 mW
0.0375 hp
0.028 kW
2.4 GHz
2,400 MHz
2,400,000 kHz
32,768 MiB
33,554,432 KiB
34,359,738,368 B
32 GiB
0.0313 TiB
Iris Graphics 550300 MHz
0.3 GHz
300,000 KHz
1,000 MHz
1 GHz
1,000,000 KHz
i3-6167USkylakeSkylake U27 September 201528 W
28,000 mW
0.0375 hp
0.028 kW
2.7 GHz
2,700 MHz
2,700,000 kHz
32,768 MiB
33,554,432 KiB
34,359,738,368 B
32 GiB
0.0313 TiB
Iris Graphics 550300 MHz
0.3 GHz
300,000 KHz
1,000 MHz
1 GHz
1,000,000 KHz
i3-6300SkylakeSkylake S27 September 201551 W
51,000 mW
0.0684 hp
0.051 kW
3.8 GHz
3,800 MHz
3,800,000 kHz
65,536 MiB
67,108,864 KiB
68,719,476,736 B
64 GiB
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
1,150 MHz
1.15 GHz
1,150,000 KHz
i3-6300TSkylakeSkylake S27 September 201535 W
35,000 mW
0.0469 hp
0.035 kW
3.3 GHz
3,300 MHz
3,300,000 kHz
65,536 MiB
67,108,864 KiB
68,719,476,736 B
64 GiB
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
950 MHz
0.95 GHz
950,000 KHz
i3-6320SkylakeSkylake S27 September 201551 W
51,000 mW
0.0684 hp
0.051 kW
3.9 GHz
3,900 MHz
3,900,000 kHz
65,536 MiB
67,108,864 KiB
68,719,476,736 B
64 GiB
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
1,150 MHz
1.15 GHz
1,150,000 KHz
i3-6320TSkylakeSkylake S35 W
35,000 mW
0.0469 hp
0.035 kW
65,536 MiB
67,108,864 KiB
68,719,476,736 B
64 GiB
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
950 MHz
0.95 GHz
950,000 KHz
i5-6198DUSkylakeSkylake U27 December 201515 W
15,000 mW
0.0201 hp
0.015 kW
2.3 GHz
2,300 MHz
2,300,000 kHz
32,768 MiB
33,554,432 KiB
34,359,738,368 B
32 GiB
0.0313 TiB
HD Graphics 510300 MHz
0.3 GHz
300,000 KHz
1,000 MHz
1 GHz
1,000,000 KHz
i5-6200USkylakeSkylake U27 September 201515 W
15,000 mW
0.0201 hp
0.015 kW
2.3 GHz
2,300 MHz
2,300,000 kHz
32,768 MiB
33,554,432 KiB
34,359,738,368 B
32 GiB
0.0313 TiB
HD Graphics 520300 MHz
0.3 GHz
300,000 KHz
1,000 MHz
1 GHz
1,000,000 KHz
i5-6260USkylakeSkylake U27 September 201515 W
15,000 mW
0.0201 hp
0.015 kW
1.8 GHz
1,800 MHz
1,800,000 kHz
32,768 MiB
33,554,432 KiB
34,359,738,368 B
32 GiB
0.0313 TiB
Iris Graphics 540300 MHz
0.3 GHz
300,000 KHz
950 MHz
0.95 GHz
950,000 KHz
i5-6267USkylakeSkylake U27 September 201528 W
28,000 mW
0.0375 hp
0.028 kW
2.9 GHz
2,900 MHz
2,900,000 kHz
32,768 MiB
33,554,432 KiB
34,359,738,368 B
32 GiB
0.0313 TiB
Iris Graphics 550300 MHz
0.3 GHz
300,000 KHz
1,050 MHz
1.05 GHz
1,050,000 KHz
i5-6287USkylakeSkylake U27 September 201528 W
28,000 mW
0.0375 hp
0.028 kW
3.1 GHz
3,100 MHz
3,100,000 kHz
32,768 MiB
33,554,432 KiB
34,359,738,368 B
32 GiB
0.0313 TiB
Iris Graphics 550300 MHz
0.3 GHz
300,000 KHz
1,100 MHz
1.1 GHz
1,100,000 KHz
i5-6300HQSkylakeSkylake H27 September 201545 W
45,000 mW
0.0603 hp
0.045 kW
2.3 GHz
2,300 MHz
2,300,000 kHz
65,536 MiB
67,108,864 KiB
68,719,476,736 B
64 GiB
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
950 MHz
0.95 GHz
950,000 KHz
i5-6300USkylakeSkylake U27 September 201515 W
15,000 mW
0.0201 hp
0.015 kW
2.4 GHz
2,400 MHz
2,400,000 kHz
32,768 MiB
33,554,432 KiB
34,359,738,368 B
32 GiB
0.0313 TiB
HD Graphics 520300 MHz
0.3 GHz
300,000 KHz
1,000 MHz
1 GHz
1,000,000 KHz
i5-6350HQSkylakeSkylake H2 January 201645 W
45,000 mW
0.0603 hp
0.045 kW
2.3 GHz
2,300 MHz
2,300,000 kHz
65,536 MiB
67,108,864 KiB
68,719,476,736 B
64 GiB
0.0625 TiB
Iris Pro Graphics 580350 MHz
0.35 GHz
350,000 KHz
900 MHz
0.9 GHz
900,000 KHz
i5-6360USkylakeSkylake U27 September 201515 W
15,000 mW
0.0201 hp
0.015 kW
2 GHz
2,000 MHz
2,000,000 kHz
32,768 MiB
33,554,432 KiB
34,359,738,368 B
32 GiB
0.0313 TiB
Iris Graphics 540300 MHz
0.3 GHz
300,000 KHz
1,000 MHz
1 GHz
1,000,000 KHz
i5-6400SkylakeSkylake S27 September 201565 W
65,000 mW
0.0872 hp
0.065 kW
2.7 GHz
2,700 MHz
2,700,000 kHz
65,536 MiB
67,108,864 KiB
68,719,476,736 B
64 GiB
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
950 MHz
0.95 GHz
950,000 KHz
i5-6400TSkylakeSkylake S27 September 201535 W
35,000 mW
0.0469 hp
0.035 kW
2.2 GHz
2,200 MHz
2,200,000 kHz
65,536 MiB
67,108,864 KiB
68,719,476,736 B
64 GiB
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
950 MHz
0.95 GHz
950,000 KHz
i5-6402PSkylakeSkylake S27 December 201565 W
65,000 mW
0.0872 hp
0.065 kW
2.8 GHz
2,800 MHz
2,800,000 kHz
65,536 MiB
67,108,864 KiB
68,719,476,736 B
64 GiB
0.0625 TiB
HD Graphics 510350 MHz
0.35 GHz
350,000 KHz
950 MHz
0.95 GHz
950,000 KHz
i5-6440EQSkylakeSkylake H12 October 201545 W
45,000 mW
0.0603 hp
0.045 kW
2.7 GHz
2,700 MHz
2,700,000 kHz
65,536 MiB
67,108,864 KiB
68,719,476,736 B
64 GiB
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
1,000 MHz
1 GHz
1,000,000 KHz
i5-6440HQSkylakeSkylake H27 October 201545 W
45,000 mW
0.0603 hp
0.045 kW
2.6 GHz
2,600 MHz
2,600,000 kHz
65,536 MiB
67,108,864 KiB
68,719,476,736 B
64 GiB
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
950 MHz
0.95 GHz
950,000 KHz
i5-6442EQSkylakeSkylake H12 October 201525 W
25,000 mW
0.0335 hp
0.025 kW
1.9 GHz
1,900 MHz
1,900,000 kHz
65,536 MiB
67,108,864 KiB
68,719,476,736 B
64 GiB
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
1,000 MHz
1 GHz
1,000,000 KHz
i5-6500SkylakeSkylake S27 September 201565 W
65,000 mW
0.0872 hp
0.065 kW
3.2 GHz
3,200 MHz
3,200,000 kHz
65,536 MiB
67,108,864 KiB
68,719,476,736 B
64 GiB
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
1,050 MHz
1.05 GHz
1,050,000 KHz
i5-6500TSkylakeSkylake S27 September 201535 W
35,000 mW
0.0469 hp
0.035 kW
2.5 GHz
2,500 MHz
2,500,000 kHz
65,536 MiB
67,108,864 KiB
68,719,476,736 B
64 GiB
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
1,100 MHz
1.1 GHz
1,100,000 KHz
i5-6500TESkylakeSkylake S19 October 201535 W
35,000 mW
0.0469 hp
0.035 kW
2.3 GHz
2,300 MHz
2,300,000 kHz
65,536 MiB
67,108,864 KiB
68,719,476,736 B
64 GiB
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
1,000 MHz
1 GHz
1,000,000 KHz
i5-6585RSkylakeSkylake H22 April 201665 W
65,000 mW
0.0872 hp
0.065 kW
2.8 GHz
2,800 MHz
2,800,000 kHz
65,536 MiB
67,108,864 KiB
68,719,476,736 B
64 GiB
0.0625 TiB
Iris Pro Graphics 580350 MHz
0.35 GHz
350,000 KHz
1,100 MHz
1.1 GHz
1,100,000 KHz
i5-6600SkylakeSkylake S27 September 201565 W
65,000 mW
0.0872 hp
0.065 kW
3.3 GHz
3,300 MHz
3,300,000 kHz
65,536 MiB
67,108,864 KiB
68,719,476,736 B
64 GiB
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
1,150 MHz
1.15 GHz
1,150,000 KHz
i5-6600KSkylakeSkylake S27 September 201591 W
91,000 mW
0.122 hp
0.091 kW
3.5 GHz
3,500 MHz
3,500,000 kHz
65,536 MiB
67,108,864 KiB
68,719,476,736 B
64 GiB
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
1,150 MHz
1.15 GHz
1,150,000 KHz
i5-6600TSkylakeSkylake S27 September 201535 W
35,000 mW
0.0469 hp
0.035 kW
2.7 GHz
2,700 MHz
2,700,000 kHz
65,536 MiB
67,108,864 KiB
68,719,476,736 B
64 GiB
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
1,100 MHz
1.1 GHz
1,100,000 KHz
i5-6685RSkylakeSkylake H22 April 201665 W
65,000 mW
0.0872 hp
0.065 kW
3.2 GHz
3,200 MHz
3,200,000 kHz
65,536 MiB
67,108,864 KiB
68,719,476,736 B
64 GiB
0.0625 TiB
Iris Pro Graphics 580350 MHz
0.35 GHz
350,000 KHz
1,150 MHz
1.15 GHz
1,150,000 KHz
i7-10510USkylakeComet Lake15 W
15,000 mW
0.0201 hp
0.015 kW
1.8 GHz
1,800 MHz
1,800,000 kHz
i7-6498DUSkylakeSkylake U27 September 201515 W
15,000 mW
0.0201 hp
0.015 kW
2.5 GHz
2,500 MHz
2,500,000 kHz
32,768 MiB
33,554,432 KiB
34,359,738,368 B
32 GiB
0.0313 TiB
HD Graphics 510300 MHz
0.3 GHz
300,000 KHz
1,050 MHz
1.05 GHz
1,050,000 KHz
i7-6500USkylakeSkylake U27 September 201515 W
15,000 mW
0.0201 hp
0.015 kW
2.5 GHz
2,500 MHz
2,500,000 kHz
32,768 MiB
33,554,432 KiB
34,359,738,368 B
32 GiB
0.0313 TiB
HD Graphics 520300 MHz
0.3 GHz
300,000 KHz
1,050 MHz
1.05 GHz
1,050,000 KHz
Count: 105

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