From WikiChip
Difference between revisions of "intel/xeon gold/6240m"
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== Memory controller == | == Memory controller == | ||
{{memory controller | {{memory controller | ||
− | |type=DDR4- | + | |type=DDR4-2400 |
|ecc=Yes | |ecc=Yes | ||
|max mem=2 TiB | |max mem=2 TiB |
Latest revision as of 07:35, 10 October 2021
Edit Values | |
Xeon Gold 6240M | |
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General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | 6240M |
S-Spec | QS25 (QS) |
Market | Server |
Introduction | April 2, 2019 (announced) April 2, 2019 (launched) |
Release Price | $5,448.00 (tray) |
Shop | Amazon |
General Specs | |
Family | Xeon Gold |
Series | 6200 |
Locked | Yes |
Frequency | 2,600 MHz |
Turbo Frequency | 3,900 MHz (1 core) |
Bus type | DMI 3.0 |
Bus rate | 4 × 8 GT/s |
Clock multiplier | 26 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Cascade Lake |
Platform | Purley |
Chipset | Lewisburg |
Core Name | Cascade Lake SP |
Core Family | 6 |
Core Model | 85 |
Core Stepping | B1 |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 18 |
Threads | 36 |
Max Memory | 2 TiB |
Multiprocessing | |
Max SMP | 4-Way (Multiprocessor) |
Interconnect | UPI |
Interconnect Links | 3 |
Interconnect Rate | 10.4 GT/s |
Electrical | |
TDP | 150 W |
Tcase | 0 °C – 85 °C |
Packaging | |
Package | FCLGA-3647 (FCLGA) |
Dimension | 76.16 mm × 56.6 mm |
Pitch | 0.8585 mm × 0.9906 mm |
Contacts | 3647 |
Socket | Socket P, LGA-3647 |
Succession | |
Xeon Gold 6240M is a 64-bit 18-core x86 high performance server microprocessor introduced by Intel in early 2019. The Gold 6240M is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 4-way multiprocessing, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor supports up 2 TiB of hexa-channel DDR4-2933 memory, operates at 2.6 GHz with a TDP of 150 W and features a turbo boost frequency of up to 3.9 GHz.
Cache[edit]
- Main article: Cascade Lake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options |
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Features[edit]
[Edit/Modify Supported Features]
Frequencies[edit]
- See also: Intel's CPU Frequency Behavior
Mode | Base | Turbo Frequency/Active Cores | |||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | ||
Normal | 2,600MHz | 3,900MHz | 3,900MHz | 3,700MHz | 3,700MHz | 3,600MHz | 3,600MHz | 3,600MHz | 3,600MHz | 3,600MHz | 3,600MHz | 3,600MHz | 3,600MHz | 3,400MHz | 3,400MHz | 3,400MHz | 3,400MHz | 3,300MHz | 3,300MHz |
AVX2 | 2,000MHz | 3,700MHz | 3,700MHz | 3,500MHz | 3,500MHz | 3,400MHz | 3,400MHz | 3,400MHz | 3,400MHz | 3,200MHz | 3,200MHz | 3,200MHz | 3,200MHz | 2,900MHz | 2,900MHz | 2,900MHz | 2,900MHz | 2,800MHz | 2,800MHz |
AVX512 | 1,600MHz | 3,700MHz | 3,700MHz | 3,500MHz | 3,500MHz | 3,400MHz | 3,400MHz | 3,400MHz | 3,400MHz | 2,900MHz | 2,900MHz | 2,900MHz | 2,900MHz | 2,600MHz | 2,600MHz | 2,600MHz | 2,600MHz | 2,500MHz | 2,500MHz |
Facts about "Xeon Gold 6240M - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Gold 6240M - Intel#pcie + |
base frequency | 2,600 MHz (2.6 GHz, 2,600,000 kHz) + |
bus links | 4 + |
bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
bus type | DMI 3.0 + |
chipset | Lewisburg + |
clock multiplier | 26 + |
core count | 18 + |
core family | 6 + |
core model | 85 + |
core name | Cascade Lake SP + |
core stepping | B1 + |
designer | Intel + |
family | Xeon Gold + |
first announced | April 2, 2019 + |
first launched | April 2, 2019 + |
full page name | intel/xeon gold/6240m + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions + and Deep Learning Boost + |
has intel deep learning boost | true + |
has intel enhanced speedstep technology | true + |
has intel speed shift technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 1,152 KiB (1,179,648 B, 1.125 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 576 KiB (589,824 B, 0.563 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 576 KiB (589,824 B, 0.563 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 18 MiB (18,432 KiB, 18,874,368 B, 0.0176 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 24.75 MiB (25,344 KiB, 25,952,256 B, 0.0242 GiB) + |
ldate | April 2, 2019 + |
main image | ![]() |
manufacturer | Intel + |
market segment | Server + |
max case temperature | 358.15 K (85 °C, 185 °F, 644.67 °R) + |
max cpu count | 4 + |
max memory | 2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) + |
max memory bandwidth | 131.13 GiB/s (134,277.12 MiB/s, 140.8 GB/s, 140,799.765 MB/s, 0.128 TiB/s, 0.141 TB/s) + |
max memory channels | 6 + |
microarchitecture | Cascade Lake + |
min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
model number | 6240M + |
name | Xeon Gold 6240M + |
package | FCLGA-3647 + |
platform | Purley + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 5,448.00 (€ 4,903.20, £ 4,412.88, ¥ 562,941.84) + |
release price (tray) | $ 5,448.00 (€ 4,903.20, £ 4,412.88, ¥ 562,941.84) + |
s-spec (qs) | QS25 + |
series | 6200 + |
smp interconnect | UPI + |
smp interconnect links | 3 + |
smp interconnect rate | 10.4 GT/s + |
smp max ways | 4 + |
socket | Socket P + and LGA-3647 + |
supported memory type | DDR4-2933 + |
tdp | 150 W (150,000 mW, 0.201 hp, 0.15 kW) + |
technology | CMOS + |
thread count | 36 + |
turbo frequency (1 core) | 3,900 MHz (3.9 GHz, 3,900,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |