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Difference between revisions of "arm holdings/microarchitectures/neoverse n2"
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− | '''Neoverse N2''' (codename ''' | + | '''Neoverse N2''' (codename '''Perseus''') is the successor to {{\\|Ares}}, a high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the server market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. |
== History == | == History == |
Latest revision as of 23:04, 25 April 2021
Edit Values | |
Zeus µarch | |
General Info | |
Arch Type | CPU |
Designer | ARM Holdings |
Manufacturer | TSMC |
Introduction | 2020 |
Process | 7 nm |
Pipeline | |
OoOE | Yes |
Speculative | Yes |
Reg Renaming | Yes |
Succession | |
Neoverse N2 (codename Perseus) is the successor to Ares, a high-performance ARM microarchitecture designed by ARM Holdings for the server market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips.
Contents
History[edit]
Zeus was first announced by Drew Henry, Arm’s SVP and GM of Infrastructure Business Unit, at his TechCon 2018 keynote.
Release Dates[edit]
Zeus is expected to show up in products around 2020.
Process Technology[edit]
Zeus specifically designed takes advantage of the power and area advantages of the 7nm+ process.
Architecture[edit]
Key changes from Ares[edit]
- 7nm+ process (from 7nm)
This list is incomplete; you can help by expanding it.
Bibliography[edit]
- Drew Henry keynote, TechCon 2018 keynote.
Facts about "Neoverse N2 - Microarchitectures - ARM"
codename | Zeus + |
designer | ARM Holdings + |
first launched | 2020 + |
full page name | arm holdings/microarchitectures/neoverse n2 + |
instance of | microarchitecture + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | Zeus + |
process | 7 nm (0.007 μm, 7.0e-6 mm) + |