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Difference between revisions of "amd/epyc/7252"
< amd‎ | epyc

(Fixed clock multiplier, added missing data, added memory bandwidth note.)
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|model number=7252
 
|model number=7252
 
|part number=100-000000080
 
|part number=100-000000080
 +
|part number 2=100-000000080WOF
 
|market=Server
 
|market=Server
 
|first announced=August 7, 2019
 
|first announced=August 7, 2019
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|frequency=3,100 MHz
 
|frequency=3,100 MHz
 
|turbo frequency=3,200 MHz
 
|turbo frequency=3,200 MHz
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|clock multiplier=28
+
|clock multiplier=31
 
|isa=x86-64
 
|isa=x86-64
 
|isa family=x86
 
|isa family=x86
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|core name=Rome
 
|core name=Rome
 
|core family=23
 
|core family=23
 +
|core model=49
 +
|core stepping=B0
 
|process=7 nm
 
|process=7 nm
 
|process 2=14 nm
 
|process 2=14 nm
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|predecessor link=amd/epyc/7251
 
|predecessor link=amd/epyc/7251
 
}}
 
}}
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'''EPYC 7252''' is a {{arch|64}} [[octa-core]] [[x86]] server microprocessor designed and introduced by [[AMD]] in mid-[[2019]]. This [[multi-chip package|multi-chip processor]], which is based on the {{amd|Zen 2|Zen 2 microarchitecture|l=arch}}, incorporates logic fabricated [[TSMC]] [[7 nm process]] and I/O fabricated on [[GlobalFoundries]] [[14 nm process]]. The 7252 has a TDP of 120 W with a base frequency of 2.8 GHz and a {{amd|precision boost|boost}} frequency of up to 3.2 GHz. This processor supports up to two-way [[symmetric multiprocessing|SMP]] and up to 4 TiB of eight channels DDR4-3200 memory per socket.
+
'''EPYC 7252''' is a {{arch|64}} [[octa-core]] [[x86]] server microprocessor designed and introduced by [[AMD]] in mid-[[2019]]. This [[multi-chip package|multi-chip processor]], which is based on the {{amd|Zen 2|Zen 2 microarchitecture|l=arch}}, incorporates two compute dies fabricated on a [[TSMC]] [[7 nm process]] and an I/O die fabricated on a [[GlobalFoundries]] [[14 nm process]]. The 7252 has a TDP of 120 W with a base frequency of 2.8 GHz and a {{amd|precision boost|boost}} frequency of up to 3.2 GHz. This processor supports up to two-way [[symmetric multiprocessing|SMP]] and up to 4 TiB of memory per socket.
  
 
== Cache ==
 
== Cache ==
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|l1d break=8x32 KiB
 
|l1d break=8x32 KiB
 
|l1d desc=8-way set associative
 
|l1d desc=8-way set associative
 +
|l1d policy=write-back
 
|l2 cache=4 MiB
 
|l2 cache=4 MiB
 
|l2 break=8x512 KiB
 
|l2 break=8x512 KiB
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== Memory controller ==
 
== Memory controller ==
 +
This model supports up to 8 channels of up to DDR4-3200 memory<ref name="specs">[https://www.amd.com/en/products/cpu/amd-epyc-7252 "AMD EPYC™ 7252"]. <i>AMD.com</i>. Retrieved October 2020.</ref><ref name="datasheet">[https://www.amd.com/system/files/documents/AMD-EPYC-7002-Series-Datasheet.pdf "AMD EPYC™ 7002 Series Processors: A New Standard for the Modern Datacenter"], AMD Publ. #LE-70002, Rev. 02, April 2020</ref> with a theoretical maximum bandwidth of 25.6 GB/s (≈ 23.84 GiB/s) per channel, but is apparently bandwidth limited by the [[amd/infinity_fabric|IFOP]] links between the I/O die and its only two compute dies (effective bandwidth ≈ 55 GB/s per CCD at 1.46 GHz FCLK<ref name="isscc2020j-chiplet">Naffziger, Samuel; Lepak, Kevin; Paraschou, Milam; Subramony, Mahesh (2020). <i>2.2 AMD Chiplet Architecture for High-Performance Server and Desktop Products</i>. 2020 IEEE International Solid-State Circuits Conference. pp. 44-45. doi:[https://doi.org/10.1109/ISSCC19947.2020.9063103 10.1109/ISSCC19947.2020.9063103]</ref>). According to AMD this processor is "optimized for 4 channels with DDR4-2667 DIMMs" (≈ 21.3 GB/s per channel) and therefore has a "per-socket theoretical memory bandwidth 85.3 GB/s" (≈ 79.47 GiB/s).<ref name="datasheet"/>
 +
 
{{memory controller
 
{{memory controller
 
|type=DDR4-3200
 
|type=DDR4-3200
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}}
 
}}
  
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== Features ==  
+
== Features ==
 
{{x86 features
 
{{x86 features
 
|real=Yes
 
|real=Yes
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|amdpbod=No
 
|amdpbod=No
 
}}
 
}}
 +
 +
== References ==
 +
<references/>

Revision as of 16:52, 4 January 2021

Edit Values
EPYC 7252
General Info
DesignerAMD
ManufacturerTSMC, GlobalFoundries
Model Number7252
Part Number100-000000080,
100-000000080WOF
MarketServer
IntroductionAugust 7, 2019 (announced)
August 7, 2019 (launched)
Release Price$475.00
ShopAmazon
General Specs
FamilyEPYC
Series7002
LockedYes
Frequency3,100 MHz
Turbo Frequency3,200 MHz
Clock multiplier31
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureZen 2
Core NameRome
Core Family23
Core Model49
Core SteppingB0
Process7 nm, 14 nm
TechnologyCMOS
MCPYes (3 dies)
Word Size64 bit
Cores8
Threads16
Max Memory4 TiB
Multiprocessing
Max SMP2-Way (Multiprocessor)
Electrical
TDP120 W
Packaging
PackageSP3, FCLGA-4094 (FC-OLGA)
Dimension75.4 mm × 58.5 mm × 6.26 mm
Pitch0.87 mm × 1 mm
Contacts4094
SocketSP3, LGA-4094
Succession

EPYC 7252 is a 64-bit octa-core x86 server microprocessor designed and introduced by AMD in mid-2019. This multi-chip processor, which is based on the Zen 2 microarchitecture, incorporates two compute dies fabricated on a TSMC 7 nm process and an I/O die fabricated on a GlobalFoundries 14 nm process. The 7252 has a TDP of 120 W with a base frequency of 2.8 GHz and a boost frequency of up to 3.2 GHz. This processor supports up to two-way SMP and up to 4 TiB of memory per socket.

Cache

Main article: Zen 2 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$512 KiB
524,288 B
0.5 MiB
L1I$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associative 
L1D$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associativewrite-back
L2$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
  8x512 KiB8-way set associativewrite-back
L3$64 MiB
65,536 KiB
67,108,864 B
0.0625 GiB
  4x16 MiB  

Memory controller

This model supports up to 8 channels of up to DDR4-3200 memory[1][2] with a theoretical maximum bandwidth of 25.6 GB/s (≈ 23.84 GiB/s) per channel, but is apparently bandwidth limited by the IFOP links between the I/O die and its only two compute dies (effective bandwidth ≈ 55 GB/s per CCD at 1.46 GHz FCLK[3]). According to AMD this processor is "optimized for 4 channels with DDR4-2667 DIMMs" (≈ 21.3 GB/s per channel) and therefore has a "per-socket theoretical memory bandwidth 85.3 GB/s" (≈ 79.47 GiB/s).[2]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-3200
Supports ECCYes
Max Mem4 TiB
Controllers8
Channels8
Max Bandwidth190.7 GiB/s
195,276.8 MiB/s
204.763 GB/s
204,762.566 MB/s
0.186 TiB/s
0.205 TB/s
Bandwidth
Single 23.84 GiB/s
Double 47.68 GiB/s
Quad 95.37 GiB/s
Hexa 143.1 GiB/s
Octa 190.7 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 4.0
Max Lanes: 128
Configuration: x16, x8


Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
SSE4aStreaming SIMD Extensions 4a
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
SHASHA Extensions
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
SMTSimultaneous Multithreading
AMD-ViAMD-Vi (I/O MMU virtualization)
AMD-VAMD Virtualization
SMESecure Memory Encryption
TSMETransparent SME
SEVSecure Encrypted Virtualization
SenseMISenseMI Technology
Boost 2Precision Boost 2

References

  1. ↑ "AMD EPYC™ 7252". AMD.com. Retrieved October 2020.
  2. ↑ 2.0 2.1 "AMD EPYC™ 7002 Series Processors: A New Standard for the Modern Datacenter", AMD Publ. #LE-70002, Rev. 02, April 2020
  3. ↑ Naffziger, Samuel; Lepak, Kevin; Paraschou, Milam; Subramony, Mahesh (2020). 2.2 AMD Chiplet Architecture for High-Performance Server and Desktop Products. 2020 IEEE International Solid-State Circuits Conference. pp. 44-45. doi:10.1109/ISSCC19947.2020.9063103
Retrieved from "https://en.wikichip.org/w/index.php?title=amd/epyc/7252&oldid=98334"
Facts about "EPYC 7252 - AMD"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
EPYC 7252 - AMD#pcie +
base frequency3,100 MHz (3.1 GHz, 3,100,000 kHz) +
clock multiplier31 +
core count8 +
core family23 +
core model49 +
core nameRome +
core steppingB0 +
designerAMD +
die count3 +
familyEPYC +
first announcedAugust 7, 2019 +
first launchedAugust 7, 2019 +
full page nameamd/epyc/7252 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has amd amd-v technologytrue +
has amd amd-vi technologytrue +
has amd precision boost 2true +
has amd secure encrypted virtualization technologytrue +
has amd secure memory encryption technologytrue +
has amd sensemi technologytrue +
has amd transparent secure memory encryption technologytrue +
has ecc memory supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, SenseMI Technology + and Precision Boost 2 +
has locked clock multipliertrue +
has simultaneous multithreadingtrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
is multi-chip packagetrue +
isax86-64 +
isa familyx86 +
l1$ size512 KiB (524,288 B, 0.5 MiB) +
l1d$ description8-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description8-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ description8-way set associative +
l2$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
l3$ size64 MiB (65,536 KiB, 67,108,864 B, 0.0625 GiB) +
ldateAugust 7, 2019 +
manufacturerTSMC + and GlobalFoundries +
market segmentServer +
max cpu count2 +
max memory4,194,304 MiB (4,294,967,296 KiB, 4,398,046,511,104 B, 4,096 GiB, 4 TiB) +
max memory bandwidth190.7 GiB/s (195,276.8 MiB/s, 204.763 GB/s, 204,762.566 MB/s, 0.186 TiB/s, 0.205 TB/s) +
max memory channels8 +
microarchitectureZen 2 +
model number7252 +
nameEPYC 7252 +
packageSP3 + and FCLGA-4094 +
part number100-000000080 + and 100-000000080WOF +
process7 nm (0.007 μm, 7.0e-6 mm) + and 14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 475.00 (€ 427.50, £ 384.75, ¥ 49,081.75) +
series7002 +
smp max ways2 +
socketSP3 + and LGA-4094 +
supported memory typeDDR4-3200 +
tdp120 W (120,000 mW, 0.161 hp, 0.12 kW) +
technologyCMOS +
thread count16 +
turbo frequency3,200 MHz (3.2 GHz, 3,200,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +