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Difference between revisions of "nervana/microarchitectures/spring crest"
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== Overview == | == Overview == | ||
| − | Spring Crest is the successor to {{\\|Knights Crest}} and is first commercial [[neural processor]] designed by Intel Nervana that made it to mass production. The chip itself is designed for training at the data center. Spring Crest is a data center training [[accelerator]], optimized for the fastest time-to-train and highest power efficiency. | + | Spring Crest is the successor to {{\\|Knights Crest}} and is first commercial [[neural processor]] designed by Intel Nervana that made it to mass production. The chip itself is designed for training at the data center. Spring Crest is a data center training [[accelerator]], optimized for the fastest time-to-train and highest power efficiency. |
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| + | == Tensor Processing Cluster (TPC) == | ||
| + | {{empty section}} | ||
| + | |||
| + | === MAC Processing Unit (MPU) === | ||
| + | {{empty section}} | ||
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| + | === Memory Subsystem === | ||
| + | {{empty section}} | ||
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| + | === Network-on-Chip (NoC) === | ||
| + | {{empty section}} | ||
== Scalability == | == Scalability == | ||
Revision as of 18:31, 9 November 2019
| Edit Values | |
| Spring Crest µarch | |
| General Info | |
| Arch Type | NPU |
| Designer | Nervana |
| Manufacturer | Intel |
| Introduction | 2019 |
| Process | 16 nm |
| PE Configs | 24 |
| Succession | |
Spring Crest (SCR) is the successor to Lake Crest, a planned neural processor microarchitecture designed by Intel Nervana.
Produces based on Spring Crest are branded as the NNP L-1000 series.
Contents
Process Technology
Spring Crest is fabricated on TSMC's 16 nm process.
Architecture
Spring Crest largely builds on the prior generation but introduces more enhancements and compute.
Key changes from Lake Crest
- 16 nm process (from 28 nm)
- 2x computer clusters (24 CCs, up from 12)
- 33% more InterChip Links (16 ICLs, up from 12)
This list is incomplete; you can help by expanding it.
Block Diagram
Chip
TCP
Overview
Spring Crest is the successor to Knights Crest and is first commercial neural processor designed by Intel Nervana that made it to mass production. The chip itself is designed for training at the data center. Spring Crest is a data center training accelerator, optimized for the fastest time-to-train and highest power efficiency.
Tensor Processing Cluster (TPC)
 |
This section is empty; you can help add the missing info by editing this page. |
MAC Processing Unit (MPU)
| |
This section is empty; you can help add the missing info by editing this page. |
Memory Subsystem
| |
This section is empty; you can help add the missing info by editing this page. |
Network-on-Chip (NoC)
| |
This section is empty; you can help add the missing info by editing this page. |
Scalability
| |
This section is empty; you can help add the missing info by editing this page. |
Package
- 60 mm x 60 mm package
- 6-2-6 layer stackup (BGA)
- 3,325 pins
- 1 die, 4 HBM 8 GiB stacks
Die
- 16 nm process
- 680 mm²
- 27,000,000,000 transistors
- 1200 mm² CoWoS
Facts about "Spring Crest - Microarchitectures - Intel Nervana"
| codename | Spring Crest + |
| designer | Nervana + |
| first launched | 2019 + |
| full page name | nervana/microarchitectures/spring crest + |
| instance of | microarchitecture + |
| manufacturer | Intel + |
| name | Spring Crest + |
| process | 16 nm (0.016 μm, 1.6e-5 mm) + |
| processing element count | 24 + |