Difference between revisions of "hisilicon/kirin/810"

	Edit Values
	Kirin 810
	General Info
Designer	HiSilicon,; ARM Holdings
Manufacturer	TSMC
Model Number	810
Market	Mobile
Introduction	June 21, 2019 (announced); June 21, 2019 (launched)
	General Specs
Family	Kirin
Series	800
Frequency	2,270 MHz, 1,880 MHz
	Microarchitecture
ISA	ARMv8 (ARM)
Microarchitecture	Cortex-A76, Cortex-A55
Core Name	Cortex-A76, Cortex-A55
Process	7 nm
Technology	CMOS
Word Size	64 bit
Cores	8
Threads	8
	Multiprocessing
Max SMP	1-Way (Uniprocessor)
	Succession
	Kirin 710

Revision as of 19:49, 23 June 2019

Kirin 810 is a 64-bit octa-core mid-range performance mobile ARM SoC introduced by HiSilicon in mid-2019. This chip, which is fabricated on TSMC's 7 nm process, features two Cortex-A76 big cores operating at up to 2.27 GHz along with six Cortex-A55 little cores operating at up to 1.88 GHz. The 810 incorporates ARM's Mali-G52 MP6 GPU.

Cache

Main articles: Cortex-A55 § Cache and Cortex-A76 § Cache

For the Cortex-A76:

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

256 KiB

262,144 B
0.25 MiB

L1I$	128 KiB 131,072 B 0.125 MiB	2x64 KiB
L1D$	128 KiB 131,072 B 0.125 MiB	2x64 KiB

L2$

1 MiB

1,024 KiB
1,048,576 B
9.765625e-4 GiB

		2x512 KiB

For the Cortex-A55:

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

384 KiB

393,216 B
0.375 MiB

L1I$	192 KiB 196,608 B 0.188 MiB	6x32 KiB
L1D$	192 KiB 196,608 B 0.188 MiB	6x32 KiB

L2$

768 KiB

0.75 MiB
786,432 B
7.324219e-4 GiB

		6x128 KiB

Memory controller

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	LPDDR4X-4266
Supports ECC	No
Max Mem	8 GiB
Controllers	1
Channels	4
Width	16 bit
Max Bandwidth	31.78 GiB/s 32,542.72 MiB/s 34.124 GB/s 34,123.515 MB/s 0.031 TiB/s 0.0341 TB/s
Bandwidth	Double 15.89 GiB/s Quad 31.78 GiB/s

Graphics

[Edit/Modify IGP Info]

Integrated Graphics Information

GPU

Mali-G52

Designer

ARM Holdings

Execution Units

6

Max Displays

2

Frequency

850 MHz

0.85 GHz
850,000 KHz

Max Resolution

	2340x1080

Hardware Acceleration
- Decode: 1080p @ 60fps
- Encode: 1080p @ 30fps

NPU

This is the first neural processing unit to use their own homegrown NPU based on Hisilicon's Da Vinci architecture.

ISP

40 MP+ 24 MP

Wireless

LTE Modem
- DL: Up to User Equipment (UE) category 21
  - Downlink of up to 1.4 Gbps (4x4 MIMO + 256QAM 3CC CA = 1.2 Gbps, 2x2 MIMI + 256QAM + 1CC = 200 Mbps)
- UL: Up to User Equipment (UE) category 18
  - Uplink of up to 200 Mbps (2x2 MIMO, 256-QAM, 1x20MHz CA)
Wi-Fi 802.11 ac
Bluetooth 5
NFC
GPS / A-GPS / GLONASS / BDS

Location

GPS, AGPS, Glonass, Beidou

Utilizing devices

Huawei Nova 5

This list is incomplete; you can help by expanding it.

@@ Line 31: / Line 31: @@
 [[File:k810.jpg|right|thumb]]
 '''Kirin 810''' is a {{arch|64}} [[octa-core]] mid-range performance mobile [[ARM]] SoC introduced by [[HiSilicon]] in mid-[[2019]]. This chip, which is fabricated on [[TSMC]]'s [[7 nm process]], features two {{armh|Cortex-A76|l=arch}} [[big cores]] operating at up to 2.27 GHz along with six {{armh|Cortex-A55}} [[little cores]] operating at up to 1.88 GHz. The 810 incorporates [[ARM Holdings|ARM]]'s {{armh|Mali-G52}} MP6 GPU.
+== Cache ==
+{{main|arm holdings/microarchitectures/cortex-a55#Memory_Hierarchy|arm holdings/microarchitectures/cortex-a76#Memory_Hierarchy|l1=Cortex-A55 § Cache|l2=Cortex-A76 § Cache}}
+For the {{armh|Cortex-A76|l=arch}}:
+{{cache size
+|l1 cache=256 KiB
+|l1i cache=128 KiB
+|l1i break=2x64 KiB
+|l1d cache=128 KiB
+|l1d break=2x64 KiB
+|l2 cache=1 MiB
+|l2 break=2x512 KiB
+}}
+For the {{armh|Cortex-A55|l=arch}}:
+{{cache size
+|l1 cache=384 KiB
+|l1i cache=192 KiB
+|l1i break=6x32 KiB
+|l1d cache=192 KiB
+|l1d break=6x32 KiB
+|l2 cache=768 KiB
+|l2 break=6x128 KiB
+}}
 == Memory controller ==
 {{memory controller
-|type=LPDDR4
+|type=LPDDR4X-4266
-|type 2=LPDDR3
 |ecc=No
-|max mem=6 GiB - 10 GIB
+|max mem=8 GiB
 |controllers=1
-|channels=2
+|channels=4
-|width=32 bit
+|width=16 bit
+|max bandwidth=31.78 GiB/s
+|bandwidth dchan=15.89 GiB/s
+|bandwidth qchan=31.78 GiB/s
 }}
 == Graphics ==
@@ Line 50: / Line 81: @@
 | max displays        = 2
 | max memory          =
-| frequency           =
+| frequency           = 850 MHz
 | max frequency       =
@@ Line 59: / Line 90: @@
 ** Decode: 1080p @ 60fps
 ** Encode: 1080p @ 30fps
+== NPU ==
+This is the first [[neural processing unit]] to use their own homegrown NPU based on Hisilicon's {{hisilicon|Da Vinci}} architecture.
 == ISP ==
 * 40 MP+ 24 MP
-== Connectivity ==
+== Wireless ==
-* WiFi
-** 802.11 a/b/g/n, 2.4GHz
-* Bluetooth 4.2
 * LTE Modem
-** Downlink
+** DL: Up to [[User Equipment]] (UE) category 21
-*** Cat-12, 600 Mbps
+*** Downlink of up to 1.4 Gbps (4x4 MIMO + 256QAM 3CC CA = 1.2 Gbps, 2x2 MIMI + 256QAM + 1CC = 200 Mbps)
-** Uplink
+** UL: Up to [[User Equipment]] (UE) category 18
-*** Cat-13, 150 Mbps
+*** Uplink of up to 200 Mbps (2x2 MIMO, 256-QAM, 1x20MHz CA)
+* Wi-Fi 802.11 ac
+* Bluetooth 5
+* NFC
+* GPS / A-GPS / GLONASS / BDS
 == Location ==

base frequency	2,270 MHz (2.27 GHz, 2,270,000 kHz) + and 1,880 MHz (1.88 GHz, 1,880,000 kHz) +
core count	8 +
core name	Cortex-A76 + and Cortex-A55 +
designer	HiSilicon + and ARM Holdings +
family	Kirin +
first announced	June 21, 2019 +
first launched	June 21, 2019 +
full page name	hisilicon/kirin/810 +
has ecc memory support	false +
instance of	microprocessor +
integrated gpu	Mali-G52 +
integrated gpu base frequency	850 MHz (0.85 GHz, 850,000 KHz) +
integrated gpu designer	ARM Holdings +
integrated gpu execution units	6 +
isa	ARMv8 +
isa family	ARM +
l1$ size	256 KiB (262,144 B, 0.25 MiB) + and 384 KiB (393,216 B, 0.375 MiB) +
l1d$ size	128 KiB (131,072 B, 0.125 MiB) + and 192 KiB (196,608 B, 0.188 MiB) +
l1i$ size	128 KiB (131,072 B, 0.125 MiB) + and 192 KiB (196,608 B, 0.188 MiB) +
l2$ size	1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + and 0.75 MiB (768 KiB, 786,432 B, 7.324219e-4 GiB) +
ldate	June 21, 2019 +
manufacturer	TSMC +
market segment	Mobile +
max cpu count	1 +
max memory bandwidth	31.78 GiB/s (32,542.72 MiB/s, 34.124 GB/s, 34,123.515 MB/s, 0.031 TiB/s, 0.0341 TB/s) +
max memory channels	4 +
microarchitecture	Cortex-A76 + and Cortex-A55 +
model number	810 +
name	Kirin 810 +
process	7 nm (0.007 μm, 7.0e-6 mm) +
series	800 +
smp max ways	1 +
supported memory type	LPDDR4X-4266 +
technology	CMOS +
thread count	8 +
used by	Huawei Nova 5 +
word size	64 bit (8 octets, 16 nibbles) +

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