Difference between revisions of "qualcomm/snapdragon 800/855"

	Edit Values
	Snapdragon 855
	General Info
Designer	Qualcomm,; ARM Holdings
Manufacturer	TSMC
Model Number	SDM855
Part Number	SM8150
Market	Mobile
Introduction	December 4, 2018 (announced); Q1, 2019 (launched)
	General Specs
Family	Snapdragon 800
Series	800
Frequency	1,800 MHz, 2,420 MHz, 2,840 MHz
	Microarchitecture
ISA	ARMv8 (ARM)
Microarchitecture	Cortex-A76, Cortex-A55
Core Name	Kryo 485 Gold, Kryo 485 Silver
Process	7 nm
Technology	CMOS
Die	73.27 mm²; 8.48 mm × 8.64 mm
Word Size	64 bit
Cores	8
Threads	8
Max Memory	16 GiB
	Multiprocessing
Max SMP	1-Way (Uniprocessor)
	Packaging
	Succession
	Snapdragon 845

Revision as of 23:13, 16 June 2019

Block Diagram

Snapdragon 855 is a high-performance 64-bit ARM LTE system on a chip designed by Qualcomm and introduced in late 2018. Fabricated on TSMC's 7nm process, the 855 features four Kryo 485 Silver high-efficiency cores operating at 1.8 GHz along with three high-performance Kryo 485 Gold operating at 2.42 GHz and another higher-performance Kryo 485 Gold core operating at 2.84 GHz. The Snapdragon 855 integrates the Adreno 640 GPU operation at ? MHz and features an X24 LTE modem supporting Cat 20 uplink and Cat 20 downlink. This chip supports up to 16 GiB of quad-channel LPDDR4X-4266 memory.

The Snapdragon 855 can be paired with Qualcomm's X50 5G modem (an external chip) and an RF front-end interface chip (RFFE) to bring 5G NR, sub-6 GHz and mmWave, support.

Cache

Main articles: Cortex-A76 § Cache and Cortex-A55 § Cache

1+3 core cluster Cortex-A76:

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

512 KiB

524,288 B
0.5 MiB

L1I$	256 KiB 262,144 B 0.25 MiB	4x64 KiB	4-way set associative
L1D$	256 KiB 262,144 B 0.25 MiB	4x64 KiB	4-way set associative

L2$

1 MiB

1,024 KiB
1,048,576 B
9.765625e-4 GiB

		4x256 KiB	8-way set associative

Quad-core cluster Cortex-A55:

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

512 KiB

524,288 B
0.5 MiB

L1I$	256 KiB 262,144 B 0.25 MiB	4x64 KiB	2-way set associative
L1D$	256 KiB 262,144 B 0.25 MiB	4x64 KiB	4-way set associative

L2$

512 KiB

0.5 MiB
524,288 B
4.882812e-4 GiB

		4x128 KiB	8-way set associative

2 MiB L3

Memory controller

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	LPDDR4X-4266
Supports ECC	No
Max Mem	16 GiB
Frequency	2133 MHz
Controllers	1
Channels	8
Width	16 bit
Max Bandwidth	31.79 GiB/s 32,552.96 MiB/s 34.134 GB/s 34,134.253 MB/s 0.031 TiB/s 0.0341 TB/s
Bandwidth	Single 7.95 GiB/s Double 15.89 GiB/s Quad 31.79 GiB/s

DSP

This chip features Qualcomm's Hexagon 685 DSP.

Graphics

[Edit/Modify IGP Info]

Integrated Graphics Information

GPU

Adreno 640 GPU

Designer

Qualcomm

Max Displays

2

Frequency

250 MHz

0.25 GHz
250,000 KHz

Burst Frequency

585 MHz

0.585 GHz
585,000 KHz

Standards

DirectX	12
OpenCL	2.0
OpenGL ES	3.2
Vulkan	1.1

Codec: H.265 (HEVC), H.264 (AVC), HDR10, HDR10+, HLG, VP8, VP9
HDR Playback Codec support for HDR10+, HDR10, HLG and Dolby Vision
Volumetric VR video playback
8K 360 VR video playback

Camera

ISP
- Qualcomm Spectra 380 image signal processor
  - Dual 14-bit CV-ISPs
  - Hardware accelerator for computer vision (CV-ISP)
- Up to 20 MP dual camera
- Up to 48 MP single camera

Photo Capture: HEIF photo capture
Video Capture:
- Rec. 2020 color gamut video capture
- Up to 10-bit color depth video capture
- Slow motion video capture up to 720p at 480fps,HEVC Video Capture

Connectivity

X24 LTE modem
- LTE Category 20
- Downlink:
  - 2 Gbps peak
  - 7x20 MHz carrier aggregation
  - Up to 256-QAM
  - Up to 4x4 MIMO on five carriers
  - Full-Dimension MIMO (FD-MIMO)
  - Maximum 20 spatial streams
- Uplink:
  - 316 Mbps peak
  - 3x20 MHz carrier aggregation
  - Up to 2x 106Mbps LTE streams
  - Up to 256-QAM
  - Uplink data compression
LTE FDD, LTE TDD including CBRS support, LAA, LTE Broadcast, WCDMA (DB-DC-HSDPA, DC-HSUPA), TD-SCDMA, CDMA 1x, EV-DO, GSM/EDGE

WiFi
- Standards: 802.11ax, 802.11ac Wave 2, 802.11a/b/g, 802.11n
- Spectral Bands: 2.4 GHz, 5 GHz, 6 GHz

Bluetooth
- Bluetooth 5.0
- 2 Mbps

Location

Systems: GPS, GLONASS, Beidou, Galileo, QZSS, SBAS, Dual frequency GNSS

Documents

Bibliography

Techinsights "Lenovo Brings the New Snapdragon to Market"

@@ Line 40: / Line 40: @@
 The Snapdragon 855 can be paired with Qualcomm's X50 5G modem (an external chip) and an RF front-end interface chip (RFFE) to bring 5G NR, sub-6 GHz and mmWave, support.
+== Cache ==
+{{main|arm_holdings/microarchitectures/cortex-a76#Memory_Hierarchy|arm_holdings/microarchitectures/cortex-a55#Memory_Hierarchy|l1=Cortex-A76 § Cache|l2=Cortex-A55 § Cache}}
++3 core cluster {{armh|Cortex-A76|l=arch}}:
+{{cache size
+|l1 cache=512 KiB
+|l1i cache=256 KiB
+|l1i break=4x64 KiB
+|l1i desc=4-way set associative
+|l1d cache=256 KiB
+|l1d break=4x64 KiB
+|l1d desc=4-way set associative
+|l2 cache=1 MiB
+|l2 break=4x256 KiB
+|l2 desc=8-way set associative
+}}
+Quad-core cluster {{armh|Cortex-A55|l=arch}}:
+{{cache size
+|l1 cache=512 KiB
+|l1i cache=256 KiB
+|l1i break=4x64 KiB
+|l1i desc=2-way set associative
+|l1d cache=256 KiB
+|l1d break=4x64 KiB
+|l1d desc=4-way set associative
+|l2 cache=512 KiB
+|l2 break=4x128 KiB
+|l2 desc=8-way set associative
+}}
+* 2 MiB L3
 == Memory controller ==

back image	+
base frequency	1,800 MHz (1.8 GHz, 1,800,000 kHz) +, 2,420 MHz (2.42 GHz, 2,420,000 kHz) + and 2,840 MHz (2.84 GHz, 2,840,000 kHz) +
core count	8 +
core name	Kryo 485 Gold + and Kryo 485 Silver +
designer	ARM Holdings + and Qualcomm +
die area	73.27 mm² (0.114 in², 0.733 cm², 73,270,000 µm²) +
die length	8.48 mm (0.848 cm, 0.334 in, 8,480 µm) +
die width	8.64 mm (0.864 cm, 0.34 in, 8,640 µm) +
dsp	Hexagon 690 DSP +
family	Snapdragon 800 +
first announced	December 4, 2018 +
first launched	March 2019 +
full page name	qualcomm/snapdragon 800/855 +
has ecc memory support	false +
instance of	microprocessor +
integrated gpu	Adreno 640 GPU +
integrated gpu base frequency	257 MHz (0.257 GHz, 257,000 KHz) +
integrated gpu designer	Qualcomm +
integrated gpu max frequency	585 MHz (0.585 GHz, 585,000 KHz) +
isa	ARMv8 +
isa family	ARM +
l1$ size	128 KiB (131,072 B, 0.125 MiB) +, 384 KiB (393,216 B, 0.375 MiB) + and 512 KiB (524,288 B, 0.5 MiB) +
l1d$ description	4-way set associative +
l1d$ size	64 KiB (65,536 B, 0.0625 MiB) +, 192 KiB (196,608 B, 0.188 MiB) + and 256 KiB (262,144 B, 0.25 MiB) +
l1i$ description	2-way set associative + and 4-way set associative +
l1i$ size	64 KiB (65,536 B, 0.0625 MiB) +, 192 KiB (196,608 B, 0.188 MiB) + and 256 KiB (262,144 B, 0.25 MiB) +
l2$ description	8-way set associative +
l2$ size	0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + and 0.75 MiB (768 KiB, 786,432 B, 7.324219e-4 GiB) +
ldate	March 2019 +
main image	+
manufacturer	TSMC +
market segment	Mobile +
max cpu count	1 +
max memory	16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB, 0.0156 TiB) +
max memory bandwidth	31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) +
max memory channels	4 +
microarchitecture	Cortex-A55 + and Cortex-A76 +
model number	SDM855 +
name	Qualcomm Snapdragon 855 +
part number	SM8150 +
process	7 nm (0.007 μm, 7.0e-6 mm) +
series	800 +
smp max ways	1 +
supported memory type	LPDDR4X-4266 +
technology	CMOS +
thread count	8 +
transistor count	6,700,000,000 +
used by	Asus ROG Phone 2 +, Asus Zenfone 6 +, Asus Zenfone 6Z +, Blackshark 2 SKywalker +, Google Pixel 4/XL +, LG G8 ThinQ +, LG G8S ThinQ +, LG G8X ThinQ +, LG V50 ThinQ +, LG V50S ThinQ +, Lenovo Z5 Pro GT +, Lenovo Z6 Pro +, Meizu 16s +, Microsoft Surface Duo +, OPPO Reno 10x Zoom +, OnePlus 7 +, OnePlus 7 Pro +, OnePlus 7T +, OnePlus 7T Pro +, Oppo Reno 10x Zoom +, Realme X2 PRO +, Samsung Galaxy A90 5G +, Samsung Galaxy Fold +, Samsung Galaxy Note 10 +, Samsung Galaxy Note 10+ +, Samsung Galaxy S10 +, Samsung Galaxy S10 5G +, Samsung Galaxy S10 Lite +, Samsung Galaxy S10+ +, Samsung Galaxy S10e +, Samsung Galaxy Tab S6 +, Sharp Aquos R3 +, Sony Xperia 1 +, Sony Xperia 5 +, VIVO IQOO +, Xiaomi Mi 9 +, Xiaomi Mi 9T Pro +, Xiaomi Mi MIX 3 5G Edition +, Xiaomi Poco X3 Pro +, Xiaomi Redmi K20 Pro +, ZTE Axon 10 Pro + and ZTE Nubia Red Magic 3 +
word size	64 bit (8 octets, 16 nibbles) +

WikiChip

The Fuse Coverage

Social Media

Companies

Microarchitectures

Technology Nodes

Intel

AMD

ARM

Cavium

Samsung

Intel

AMD

Ampere

Apple

Cavium

HiSilicon

MediaTek

NXP

Qualcomm

Renesas

Samsung

Revision as of 23:13, 16 June 2019

Contents

Cache

Memory controller

DSP

Graphics

Camera

Connectivity

Location

Documents

Bibliography