Latest revision as of 12:56, 9 May 2019

Palm Cove is a high-performance 10 nm x86 core microarchitecture designed by Intel for an array of server and client products.

Process Technology[edit]

Palm Cove is designed to take advantage of Intel's 10 nm process.

Architecture[edit]

Key changes from Skylake (Client)[edit]

• 10 nm process (From 14 nm)
• Front End
  • LSD is re-enabled (See Skylake § Front-end for details)
  • 50% smaller L1 instruction cache 4K page TLB (64-entry, down from 128)
• Back-end
  • Execution units
    • Port 4 now performs 512b stores (from 256b)
    • New 512b FMA unit on Port 0
    • New iDIV unit
• Memory subsystem
  • Store is now 64B/cycle (from 32B/cycle)
  • Load is now 2x64B/cycle (from 2x32B/cycle)

This list is incomplete; you can help by expanding it.

New instructions[edit]

Cannon Lake introduced a number of new instructions:

• AVX-512, specifically:
  • AVX512F - AVX-512 Foundation
  • AVX512CD - AVX-512 Conflict Detection
  • AVX512BW - AVX-512 Byte and Word
  • AVX512DQ - AVX-512 Doubleword and Quadword
  • AVX512VL - AVX-512 Vector Length
  • AVX512IFMA - AVX-512 Integer Fused Multiply-Add
  • AVX512VBMI - AVX-512 Vector Bit Manipulation
• SHA - Hardware acceleration for SHA hashing operations
• UMIP - User-Mode Instruction Prevention extension

Memory Hierarchy[edit]

Other than a few organizational changes (e.g. L2$ went from 8-way to 4-way set associative), the overall memory structure is identical to Broadwell/Haswell.

• Cache
  • L0 µOP cache:
    • 1,536 µOPs, 8-way set associative
      • 32 sets, 6-µOP line size
      • statically divided between threads, per core, inclusive with L1I
  • L1I Cache:
    • 32 KiB, 8-way set associative
      • 64 sets, 64 B line size
      • shared by the two threads, per core
  • L1D Cache:
    • 32 KiB, 8-way set associative
    • 64 sets, 64 B line size
    • shared by the two threads, per core
    • 4 cycles for fastest load-to-use (simple pointer accesses)
      • 5 cycles for complex addresses
    • 128 B/cycle load bandwidth
    • 64 B/cycle store bandwidth
    • Write-back policy
  • L2 Cache:
    • Unified, 256 KiB, 4-way set associative
    • 1024 sets, 64 B line size
    • Non-inclusive
    • 12 cycles for fastest load-to-use
    • 64 B/cycle bandwidth to L1$
    • Write-back policy
  • L3 Cache/LLC:
    • Up to 2 MiB Per core, shared across all cores
    • Up to 16-way set associative
    • Inclusive
    • 64 B line size
    • Write-back policy
    • Per each core:
      • Read: 32 B/cycle (@ ring clock)
      • Write: 32 B/cycle (@ ring clock)
    • 42 cycles for fastest load-to-use
  • System DRAM:
    • 2 Channels
    • 8 B/cycle/channel (@ memory clock)

Palm Cove TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB).

• TLBs:
  • ITLB
    • 4 KiB page translations:
      • 64 entries; 8-way set associative
      • dynamic partitioning
    • 2 MiB / 4 MiB page translations:
      • 8 entries per thread; fully associative
      • Duplicated for each thread
  • DTLB
    • 4 KiB page translations:
      • 64 entries; 4-way set associative
      • fixed partition
    • 2 MiB / 4 MiB page translations:
      • 32 entries; 4-way set associative
      • fixed partition
    • 1G page translations:
      • 4 entries; 4-way set associative
      • fixed partition
  • STLB
    • 4 KiB + 2 MiB page translations:
      • 1536 entries; 12-way set associative
      • fixed partition
    • 1 GiB page translations:
      • 16 entries; 4-way set associative
      • fixed partition

Overview[edit]

Palm Cove is the core microarchitecture that is found in Intel's Cannon Lake SoCs. Although originally intended to be mass manufactured for all client and server markets, due to Intel's prolong 10 nm process problems, Palm Cove is getting skipped with the exception of a single chip.

See also[edit]

• Cannon Lake