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Difference between revisions of "intel/xeon gold/5215l"
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|amdpb2=No
 
|amdpb2=No
 
|amdpbod=No
 
|amdpbod=No
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}}
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== Frequencies ==
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{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
 +
{{frequency table
 +
|freq_base=2,500MHz
 +
|freq_1=3,400MHz
 +
|freq_2=3,400MHz
 +
|freq_3=3,200MHz
 +
|freq_4=3,200MHz
 +
|freq_5=3,100MHz
 +
|freq_6=3,100MHz
 +
|freq_7=3,100MHz
 +
|freq_8=3,100MHz
 +
|freq_9=3,000MHz
 +
|freq_10=3,000MHz
 +
|freq_avx2_base=2,000MHz
 +
|freq_avx2_1=3,100MHz
 +
|freq_avx2_2=3,100MHz
 +
|freq_avx2_3=2,900MHz
 +
|freq_avx2_4=2,900MHz
 +
|freq_avx2_5=2,800MHz
 +
|freq_avx2_6=2,800MHz
 +
|freq_avx2_7=2,800MHz
 +
|freq_avx2_8=2,800MHz
 +
|freq_avx2_9=2,600MHz
 +
|freq_avx2_10=2,600MHz
 +
|freq_avx512_base=1,400MHz
 +
|freq_avx512_1=2,900MHz
 +
|freq_avx512_2=2,900MHz
 +
|freq_avx512_3=2,500MHz
 +
|freq_avx512_4=2,500MHz
 +
|freq_avx512_5=1,900MHz
 +
|freq_avx512_6=1,900MHz
 +
|freq_avx512_7=1,900MHz
 +
|freq_avx512_8=1,900MHz
 +
|freq_avx512_9=1,800MHz
 +
|freq_avx512_10=1,800MHz
 
}}
 
}}

Revision as of 01:40, 8 May 2019

Edit Values
Xeon Gold 5215L
cascade lake sp (front).png
General Info
DesignerIntel
ManufacturerIntel
Model Number5215L
Part NumberCD8069504214202
S-SpecSRFBD
MarketServer
IntroductionApril 2, 2019 (announced)
April 2, 2019 (launched)
Release Price$4,224.00 (tray)
ShopAmazon
General Specs
FamilyXeon Gold
Series5200
LockedYes
Frequency2,500 MHz
Turbo Frequency3,400 MHz (1 core)
Bus typeDMI 3.0
Bus rate4 × 8 GT/s
Clock multiplier25
CPUID0x50655
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureCascade Lake
PlatformPurley
ChipsetLewisburg
Core NameCascade Lake SP
Core Family6
Core SteppingL1
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores10
Threads20
Max Memory4.5 TiB
Multiprocessing
Max SMP4-Way (Multiprocessor)
Electrical
TDP85 W
Packaging
PackageFCLGA-3647 (FCLGA)
Dimension76.16 mm × 56.6 mm
Pitch0.8585 mm × 0.9906 mm
Contacts3647
SocketSocket P, LGA-3647

Xeon Gold 5215L is a 64-bit deca-core x86 high performance server microprocessor introduced by Intel in early 2019. The Gold 5215L is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 4-way multiprocessing, sports one AVX-512 FMA units as well as three UPI links. This microprocessor supports up 4.5 TiB of hexa-channel DDR4-2666 memory, operates at 2.2 GHz with a TDP of 125 W and features a turbo boost frequency of up to 3.9 GHz.

As indicated by the "L" suffix, this model features extended memory support of up to 4.5 TiB of memory.


Cache

Main article: Cascade Lake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$640 KiB
655,360 B
0.625 MiB
L1I$320 KiB
327,680 B
0.313 MiB
10x32 KiB8-way set associative 
L1D$320 KiB
327,680 B
0.313 MiB
10x32 KiB8-way set associativewrite-back
L2$10 MiB
10,240 KiB
10,485,760 B
0.00977 GiB
  10x1 MiB16-way set associativewrite-back
L3$13.75 MiB
14,080 KiB
14,417,920 B
0.0134 GiB
  10x1.375 MiB11-way set associativewrite-back

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2666
Supports ECCYes
Max Mem4.5 TiB
Controllers2
Channels6
Max Bandwidth119.21 GiB/s
122,071.04 MiB/s
128.001 GB/s
128,000.763 MB/s
0.116 TiB/s
0.128 TB/s
Bandwidth
Single 19.87 GiB/s
Double 39.74 GiB/s
Quad 79.47 GiB/s
Hexa 119.21 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 48
Configuration: 1x16, x8, x4


Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
AVX-512Advanced Vector 512-bit
AVX512FAVX-512 Foundation
AVX512CDAVX-512 Conflict Detection
AVX512BWAVX-512 Byte and Word
AVX512DQAVX-512 Doubleword and Quadword Instructions
AVX512VLAVX-512 Vector Length
AVX512_VNNIAVX-512 Vector Neural Network Instructions
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
TXTTrusted Execution Technology (SMX)
vProIntel vPro
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
VMDVolume Management Device
NMNode Manager
KPTKey Protection Technology
PTTPlatform Trust Technology
MBE CtrlMode-Based Execute Control
DL BoostDeep Learning Boost

Frequencies

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

ModeBaseTurbo Frequency/Active Cores
12345678910
Normal2,500MHz3,400MHz3,400MHz3,200MHz3,200MHz3,100MHz3,100MHz3,100MHz3,100MHz3,000MHz3,000MHz
AVX22,000MHz3,100MHz3,100MHz2,900MHz2,900MHz2,800MHz2,800MHz2,800MHz2,800MHz2,600MHz2,600MHz
AVX5121,400MHz2,900MHz2,900MHz2,500MHz2,500MHz1,900MHz1,900MHz1,900MHz1,900MHz1,800MHz1,800MHz
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_gold/5215l&oldid=90134"
Facts about "Xeon Gold 5215L - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon Gold 5215L - Intel#pcie +
base frequency2,500 MHz (2.5 GHz, 2,500,000 kHz) +
bus links4 +
bus rate8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus typeDMI 3.0 +
chipsetLewisburg +
clock multiplier25 +
core count10 +
core family6 +
core nameCascade Lake SP +
core steppingL1 +
cpuid0x50655 +
designerIntel +
familyXeon Gold +
first announcedApril 2, 2019 +
first launchedApril 2, 2019 +
full page nameintel/xeon gold/5215l +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has advanced vector extensions 512true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions + and Deep Learning Boost +
has intel deep learning boosttrue +
has intel enhanced speedstep technologytrue +
has intel speed shift technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size640 KiB (655,360 B, 0.625 MiB) +
l1d$ description8-way set associative +
l1d$ size320 KiB (327,680 B, 0.313 MiB) +
l1i$ description8-way set associative +
l1i$ size320 KiB (327,680 B, 0.313 MiB) +
l2$ description16-way set associative +
l2$ size10 MiB (10,240 KiB, 10,485,760 B, 0.00977 GiB) +
l3$ description11-way set associative +
l3$ size13.75 MiB (14,080 KiB, 14,417,920 B, 0.0134 GiB) +
ldateApril 2, 2019 +
main imageFile:cascade lake sp (front).png +
manufacturerIntel +
market segmentServer +
max cpu count4 +
max memory4,718,592 MiB (4,831,838,208 KiB, 4,947,802,324,992 B, 4,608 GiB, 4.5 TiB) +
max memory bandwidth119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels6 +
microarchitectureCascade Lake +
model number5215L +
nameXeon Gold 5215L +
packageFCLGA-3647 +
part numberCD8069504214202 +
platformPurley +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 4,224.00 (€ 3,801.60, £ 3,421.44, ¥ 436,465.92) +
release price (tray)$ 4,224.00 (€ 3,801.60, £ 3,421.44, ¥ 436,465.92) +
s-specSRFBD +
series5200 +
smp max ways4 +
socketSocket P + and LGA-3647 +
supported memory typeDDR4-2666 +
tdp85 W (85,000 mW, 0.114 hp, 0.085 kW) +
technologyCMOS +
thread count20 +
turbo frequency (1 core)3,400 MHz (3.4 GHz, 3,400,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +