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'''Xeon Gold 6248''' is a {{arch|64}} [[20-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 6248 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 2.5 GHz with a TDP of 150 W and features a {{intel|turbo boost}} frequency of up to 3.9 GHz.
 
'''Xeon Gold 6248''' is a {{arch|64}} [[20-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 6248 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 2.5 GHz with a TDP of 150 W and features a {{intel|turbo boost}} frequency of up to 3.9 GHz.
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== Cache ==
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{{main|intel/microarchitectures/cascade lake#Memory_Hierarchy|l1=Cascade Lake § Cache}}
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{{cache size
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|l1 cache=1.25 MiB
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|l1i cache=640 KiB
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|l1i break=20x32 KiB
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|l1i desc=8-way set associative
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|l1d cache=640 KiB
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|l1d break=20x32 KiB
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|l1d desc=8-way set associative
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|l1d policy=write-back
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|l2 cache=20 MiB
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|l2 break=20x1 MiB
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|l2 desc=16-way set associative
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|l2 policy=write-back
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|l3 cache=27.5 MiB
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|l3 break=20x1.375 MiB
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|l3 desc=11-way set associative
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|l3 policy=write-back
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}}

Revision as of 20:55, 7 May 2019

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General Info
Microarchitecture

Xeon Gold 6248 is a 64-bit 20-core x86 high performance server microprocessor introduced by Intel in early 2019. The Gold 6248 is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 4-way multiprocessing, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 2.5 GHz with a TDP of 150 W and features a turbo boost frequency of up to 3.9 GHz.


Cache

Main article: Cascade Lake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1.25 MiB
1,280 KiB
1,310,720 B
L1I$640 KiB
655,360 B
0.625 MiB
20x32 KiB8-way set associative 
L1D$640 KiB
655,360 B
0.625 MiB
20x32 KiB8-way set associativewrite-back
L2$20 MiB
20,480 KiB
20,971,520 B
0.0195 GiB
  20x1 MiB16-way set associativewrite-back
L3$27.5 MiB
28,160 KiB
28,835,840 B
0.0269 GiB
  20x1.375 MiB11-way set associativewrite-back
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Facts about "Xeon Gold 6248 - Intel"
RDF feed
full page nameintel/xeon gold/6248 +
instance ofmicroprocessor +
l1$ size1,280 KiB (1,310,720 B, 1.25 MiB) +
l1d$ description8-way set associative +
l1d$ size640 KiB (655,360 B, 0.625 MiB) +
l1i$ description8-way set associative +
l1i$ size640 KiB (655,360 B, 0.625 MiB) +
l2$ description16-way set associative +
l2$ size20 MiB (20,480 KiB, 20,971,520 B, 0.0195 GiB) +
l3$ description11-way set associative +
l3$ size27.5 MiB (28,160 KiB, 28,835,840 B, 0.0269 GiB) +
ldate1900 +