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Difference between revisions of "hisilicon/microarchitectures/taishan v110"
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{{hisilicon|TaiShan|l=arch}} | {{hisilicon|TaiShan|l=arch}} | ||
| − | {{microarchitecture}} | + | {{microarchitecture |
| + | |atype=CPU | ||
| + | |name=TaiShan | ||
| + | |designer=HiSilicon | ||
| + | |manufacturer=TSMC | ||
| + | |introduction=2018 | ||
| + | |process=7 nm | ||
| + | |cores=32 | ||
| + | |cores 2=48 | ||
| + | |cores 3=64 | ||
| + | |type=Superscalar | ||
| + | |type 2=Superpipeline | ||
| + | |oooe=Yes | ||
| + | |speculative=Yes | ||
| + | |renaming=Yes | ||
| + | |decode=4-way | ||
| + | |isa=ARMv8.2-A | ||
| + | |feature=Hardware compression accelerator | ||
| + | |feature 2=Hardware cryptography accelerator | ||
| + | |extension=NEON | ||
| + | |l1i=64 KiB | ||
| + | |l1i per=core | ||
| + | |l1d=64 KiB | ||
| + | |l1d per=core | ||
| + | |l2=512 KiB | ||
| + | |l2 per=core | ||
| + | |l3=1 MiB | ||
| + | |l3 per=core | ||
| + | |core name=TaiShan | ||
| + | }} | ||
'''TaiShan''' is a high-performance [[ARM]] server microarchitecture designed by [[HiSilicon]] for [[Huawei]]'s own TaiShan servers. | '''TaiShan''' is a high-performance [[ARM]] server microarchitecture designed by [[HiSilicon]] for [[Huawei]]'s own TaiShan servers. | ||
Revision as of 11:55, 2 May 2019
| Edit Values | |
| TaiShan µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | HiSilicon |
| Manufacturer | TSMC |
| Introduction | 2018 |
| Process | 7 nm |
| Core Configs | 32, 48, 64 |
| Pipeline | |
| Type | Superscalar, Superpipeline |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Decode | 4-way |
| Instructions | |
| ISA | ARMv8.2-A |
| Extensions | NEON |
| Cache | |
| L1I Cache | 64 KiB/core |
| L1D Cache | 64 KiB/core |
| L2 Cache | 512 KiB/core |
| L3 Cache | 1 MiB/core |
| Cores | |
| Core Names | TaiShan |
TaiShan is a high-performance ARM server microarchitecture designed by HiSilicon for Huawei's own TaiShan servers.
Facts about "TaiShan v110 - Microarchitectures - HiSilicon"
| codename | TaiShan + |
| core count | 32 +, 48 + and 64 + |
| designer | HiSilicon + |
| first launched | 2018 + |
| full page name | hisilicon/microarchitectures/taishan v110 + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv8.2-A + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | TaiShan + |
| process | 7 nm (0.007 μm, 7.0e-6 mm) + |