From WikiChip
Difference between revisions of "intel/xeon silver/4209t"
< intel‎ | xeon silver

Line 73: Line 73:
 
|bandwidth qchan=71.53 GiB/s
 
|bandwidth qchan=71.53 GiB/s
 
|bandwidth hchan=107.3 GiB/s
 
|bandwidth hchan=107.3 GiB/s
 +
}}
 +
 +
== Expansions ==
 +
{{expansions main
 +
|
 +
{{expansions entry
 +
|type=PCIe
 +
|pcie revision=3.0
 +
|pcie lanes=40
 +
|pcie config=1x16
 +
|pcie config 2=2x8
 +
|pcie config 3=1x8+2x4
 +
}}
 
}}
 
}}

Revision as of 19:41, 3 April 2019

Edit Values
Xeon Silver 4209T
cascade lake sp (front).png
General Info
DesignerIntel
ManufacturerIntel
Model Number4209T
Part NumberCD8069503956900
S-SpecSRFBQ
MarketServer
IntroductionApril 2, 2019 (announced)
April 2, 2019 (launched)
Release Price$501.00 (tray)
ShopAmazon
General Specs
FamilyXeon Silver
Series4200
LockedYes
Frequency2,200 MHz
Turbo Frequency3,200 MHz (1 core)
Clock multiplier22
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureCascade Lake
PlatformPurley
ChipsetLewisburg
Core NameCascade Lake SP
Core Family6
Core SteppingR1
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores8
Threads16
Multiprocessing
Max SMP2-Way (Multiprocessor)
Electrical
TDP70 W
Tcase0 °C – 91 °C
Packaging
PackageFCLGA-3647 (FCLGA)
Dimension76.16 mm × 56.6 mm
Pitch0.8585 mm × 0.9906 mm
Contacts3647
SocketSocket P, LGA-3647

Xeon Silver 4209T is a 64-bit octa-core x86 mid-range performance server microprocessor introduced by Intel in early 2019. The Silver 4209T is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports dual-way multiprocessing, sports one AVX-512 FMA units as well as two UPI links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2400 memory, operates at 2.2 GHz with a TDP of 70 W and features a turbo boost frequency of up to 3.2 GHz.


Cache

Main article: Cascade Lake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$512 KiB
524,288 B
0.5 MiB
L1I$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associative 
L1D$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associativewrite-back
L2$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  8x1 MiB16-way set associativewrite-back
L3$11 MiB
11,264 KiB
11,534,336 B
0.0107 GiB
  8x1.375 MiB11-way set associativewrite-back

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2400
Supports ECCYes
Max Mem1 TiB
Controllers2
Channels6
Max Bandwidth107.3 GiB/s
109,875.2 MiB/s
115.212 GB/s
115,212.498 MB/s
0.105 TiB/s
0.115 TB/s
Bandwidth
Single 17.88 GiB/s
Double 35.76 GiB/s
Quad 71.53 GiB/s
Hexa 107.3 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 40
Configuration: 1x16, 2x8, 1x8+2x4
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_silver/4209t&oldid=87884"
Facts about "Xeon Silver 4209T - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon Silver 4209T - Intel#pcie +
base frequency2,200 MHz (2.2 GHz, 2,200,000 kHz) +
chipsetLewisburg +
clock multiplier22 +
core count8 +
core family6 +
core nameCascade Lake SP +
core steppingR1 +
designerIntel +
familyXeon Silver +
first announcedApril 2, 2019 +
first launchedApril 2, 2019 +
full page nameintel/xeon silver/4209t +
has ecc memory supporttrue +
has locked clock multipliertrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size512 KiB (524,288 B, 0.5 MiB) +
l1d$ description8-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description8-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ description16-way set associative +
l2$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
l3$ description11-way set associative +
l3$ size11 MiB (11,264 KiB, 11,534,336 B, 0.0107 GiB) +
ldateApril 2, 2019 +
main imageFile:cascade lake sp (front).png +
manufacturerIntel +
market segmentServer +
max case temperature364.15 K (91 °C, 195.8 °F, 655.47 °R) +
max cpu count2 +
max memory bandwidth107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) +
max memory channels6 +
microarchitectureCascade Lake +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
model number4209T +
nameXeon Silver 4209T +
packageFCLGA-3647 +
part numberCD8069503956900 +
platformPurley +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 501.00 (€ 450.90, £ 405.81, ¥ 51,768.33) +
release price (tray)$ 501.00 (€ 450.90, £ 405.81, ¥ 51,768.33) +
s-specSRFBQ +
series4200 +
smp max ways2 +
socketSocket P + and LGA-3647 +
supported memory typeDDR4-2400 +
tdp70 W (70,000 mW, 0.0939 hp, 0.07 kW) +
technologyCMOS +
thread count16 +
turbo frequency (1 core)3,200 MHz (3.2 GHz, 3,200,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +