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Difference between revisions of "arm holdings/microarchitectures/cortex-a9"
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|successor 2=Cortex-A7
 
|successor 2=Cortex-A7
 
|successor 2 link=arm_holdings/microarchitectures/cortex-a7
 
|successor 2 link=arm_holdings/microarchitectures/cortex-a7
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|successor 3=Cortex-A12
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|successor 3 link=arm_holdings/microarchitectures/cortex-a12
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|successor 4=Cortex-A5
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|successor 4 link=arm_holdings/microarchitectures/cortex-a5
 
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'''Cortex-A9''' is the successor to the {{armh|Cortex-A8|l=arch}}, a low-power performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips.
 
'''Cortex-A9''' is the successor to the {{armh|Cortex-A8|l=arch}}, a low-power performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips.
  
 
The Cortex-A9 was later succeeded by three independent lines - high-performance ({{\\|Cortex-A15|A15}}), mainstream performance ({{\\|Cortex-A12|A12}}), and high efficiency ({{\\|Cortex-A7|A7}}.
 
The Cortex-A9 was later succeeded by three independent lines - high-performance ({{\\|Cortex-A15|A15}}), mainstream performance ({{\\|Cortex-A12|A12}}), and high efficiency ({{\\|Cortex-A7|A7}}.

Revision as of 07:09, 29 December 2018

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Cortex-A9 µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerTSMC
IntroductionOctober 3, 2007
Process40 nm
Succession

Cortex-A9 is the successor to the Cortex-A8, a low-power performance ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips.

The Cortex-A9 was later succeeded by three independent lines - high-performance (A15), mainstream performance (A12), and high efficiency (A7.

codenameCortex-A9 +
designerARM Holdings +
first launchedOctober 3, 2007 +
full page namearm holdings/microarchitectures/cortex-a9 +
instance ofmicroarchitecture +
instruction set architectureARMv7 +
manufacturerTSMC +
microarchitecture typeCPU +
nameCortex-A9 +
process40 nm (0.04 μm, 4.0e-5 mm) +