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'''Cortex-A76''' (codename '''Enyo''') is the successor to the {{armh|Cortex-A75|l=arch}}, a low-power high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A76, which implemented the {{arm|ARMv8.2}} ISA, is the a performant core which is often combined with a number of lower power cores (e.g. {{\\|Cortex-A55}}) in a {{armh|DynamIQ big.LITTLE}} configuration to achieve better energy/performance.
 
'''Cortex-A76''' (codename '''Enyo''') is the successor to the {{armh|Cortex-A75|l=arch}}, a low-power high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A76, which implemented the {{arm|ARMv8.2}} ISA, is the a performant core which is often combined with a number of lower power cores (e.g. {{\\|Cortex-A55}}) in a {{armh|DynamIQ big.LITTLE}} configuration to achieve better energy/performance.
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== Architecture ==
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=== Key changes from {{\\|Cortex-A75}} ===
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=== Block Diagram ===
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==== Typical SoC ====
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:[[File:cortex-a76 soc block diagram.svg|550px]]
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==== Individual Core ====
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:[[File:cortex-a76 block diagram.svg|850px]]

Revision as of 01:16, 27 December 2018

Edit Values
Cortex-A76 µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerTSMC
IntroductionMay 31, 2018
Process10 nm, 7 nm
Core Configs1, 2, 4
Pipeline
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages11-13
Decode4-way
Instructions
ISAARMv8.2
ExtensionsFPU, NEON
Cache
L1I Cache8-64 KiB/core
4-way set associative
L1D Cache8-64 KiB/core
4-way set associative
L2 Cache64-256-512 KiB/core
L3 Cache0-4 MiB/Cluster
Succession
Contemporary
Ares

Cortex-A76 (codename Enyo) is the successor to the Cortex-A75, a low-power high-performance ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A76, which implemented the ARMv8.2 ISA, is the a performant core which is often combined with a number of lower power cores (e.g. Cortex-A55) in a DynamIQ big.LITTLE configuration to achieve better energy/performance.

Architecture

Key changes from Cortex-A75

Block Diagram

Typical SoC

cortex-a76 soc block diagram.svg

Individual Core

cortex-a76 block diagram.svg
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Facts about "Cortex-A76 - Microarchitectures - ARM"
RDF feed
codenameCortex-A76 +
core count1 +, 2 + and 4 +
designerARM Holdings +
first launchedMay 31, 2018 +
full page namearm holdings/microarchitectures/cortex-a76 +
instance ofmicroarchitecture +
instruction set architectureARMv8.2 +
manufacturerTSMC +
microarchitecture typeCPU +
nameCortex-A76 +
pipeline stages (max)13 +
pipeline stages (min)11 +
process10 nm (0.01 μm, 1.0e-5 mm) + and 7 nm (0.007 μm, 7.0e-6 mm) +