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Difference between revisions of "qualcomm/snapdragon 800/8cx"
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'''Snapdragon 8cx''' ('''Snapdragon 8 Compute eXtreme''') is a high-performance {{arch|64}} [[ARM]] [[LTE]] [[system on a chip]] designed by [[Qualcomm]] and introduced in late [[2018]]. Fabricated on TSMC's [[7nm process]], the 8cx features four [[Kryo 495 Silver]] high-efficiency cores operating at ? GHz along with two high-performance [[Kryo 495 Gold]] operating at ? GHz. The Snapdragon 8cx integrates the {{qualcomm|Adreno 680}} [[GPU]] operation at ? MHz and features an X24 LTE modem supporting Cat 20 uplink and Cat 20 downlink. This chip supports up to ? GiB of octa-channel LPDDR4X-4266 memory.
 
'''Snapdragon 8cx''' ('''Snapdragon 8 Compute eXtreme''') is a high-performance {{arch|64}} [[ARM]] [[LTE]] [[system on a chip]] designed by [[Qualcomm]] and introduced in late [[2018]]. Fabricated on TSMC's [[7nm process]], the 8cx features four [[Kryo 495 Silver]] high-efficiency cores operating at ? GHz along with two high-performance [[Kryo 495 Gold]] operating at ? GHz. The Snapdragon 8cx integrates the {{qualcomm|Adreno 680}} [[GPU]] operation at ? MHz and features an X24 LTE modem supporting Cat 20 uplink and Cat 20 downlink. This chip supports up to ? GiB of octa-channel LPDDR4X-4266 memory.
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== Overview ==
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The Snapdragon 8cx was announced by [[Qualcomm]] on December 6, 2018. The chip is what Qualcomm considers a new high tier Snapdragon aimed at always-connected PCs with higher performance and thermal headroom over traditional smartphone devices. The chip comprise of a quad-core cluster of [[Kryo 495 Gold]] ([[Cortex-A76]]) [[big cores]] and a quad-core cluster of [[Kryo 495 Silver]] ([[Cortex-A55]]) [[little cores]].
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== Cache ==
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{{main|arm_holdings/microarchitectures/cortex-a76#Memory_Hierarchy|arm_holdings/microarchitectures/cortex-a55#Memory_Hierarchy|l1=Cortex-A76 § Cache|l2=Cortex-A55}}
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{{cache size
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|l3 cache=10 MiB
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|l3 break=1x10 MiB
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}}
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== Memory controller ==
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{{memory controller
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|type=LPDDR4X-4266
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|ecc=No
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|max mem=? GiB
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|controllers=1
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|channels=8
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|width=16 bit
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|max bandwidth=29.87 GiB/s
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|frequency=2133 MHz
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|bandwidth schan=7.95 GiB/s
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|bandwidth dchan=15.89 GiB/s
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|bandwidth qchan=31.79 GiB/s
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|bandwidth ochan=63.58 GiB/s
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}}

Revision as of 22:10, 6 December 2018

Edit Values
Snapdragon 8cx
sd 8cx (front).png
General Info
DesignerQualcomm,
ARM Holdings
ManufacturerTSMC
MarketMobile
IntroductionDecember 6, 2018 (announced)
Q3, 2019 (launched)
General Specs
FamilySnapdragon 800
Series800
Microarchitecture
ISAARMv8 (ARM)
MicroarchitectureCortex-A76, Cortex-A55
Core NameCortex-A76, Cortex-A55
Process7 nm
TechnologyCMOS
Word Size64 bit
Cores8
Threads8
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
TDP7 W
Packaging
sd 8cx (back).png
Succession

Snapdragon 8cx (Snapdragon 8 Compute eXtreme) is a high-performance 64-bit ARM LTE system on a chip designed by Qualcomm and introduced in late 2018. Fabricated on TSMC's 7nm process, the 8cx features four Kryo 495 Silver high-efficiency cores operating at ? GHz along with two high-performance Kryo 495 Gold operating at ? GHz. The Snapdragon 8cx integrates the Adreno 680 GPU operation at ? MHz and features an X24 LTE modem supporting Cat 20 uplink and Cat 20 downlink. This chip supports up to ? GiB of octa-channel LPDDR4X-4266 memory.

Overview

The Snapdragon 8cx was announced by Qualcomm on December 6, 2018. The chip is what Qualcomm considers a new high tier Snapdragon aimed at always-connected PCs with higher performance and thermal headroom over traditional smartphone devices. The chip comprise of a quad-core cluster of Kryo 495 Gold (Cortex-A76) big cores and a quad-core cluster of Kryo 495 Silver (Cortex-A55) little cores.

Cache

Main articles: Cortex-A76 § Cache and Cortex-A55

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L3$10 MiB
10,240 KiB
10,485,760 B
0.00977 GiB
  1x10 MiB  

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR4X-4266
Supports ECCNo
Max Mem? GiB
Frequency2133 MHz
Controllers1
Channels8
Width16 bit
Max Bandwidth29.87 GiB/s
30,586.88 MiB/s
32.073 GB/s
32,072.668 MB/s
0.0292 TiB/s
0.0321 TB/s
Bandwidth
Single 7.95 GiB/s
Double 15.89 GiB/s
Quad 31.79 GiB/s
Octa 63.58 GiB/s
Retrieved from "https://en.wikichip.org/w/index.php?title=qualcomm/snapdragon_800/8cx&oldid=84661"
Facts about "Snapdragon 8cx - Qualcomm"
RDF feed
back imageFile:sd 8cx (back).png +
core count8 +
core nameCortex-A76 + and Cortex-A55 +
designerQualcomm + and ARM Holdings +
familySnapdragon 800 +
first announcedDecember 6, 2018 +
first launchedMarch 2019 +
full page namequalcomm/snapdragon 800/8cx +
has ecc memory supportfalse +
instance ofmicroprocessor +
isaARMv8 +
isa familyARM +
l3$ size10 MiB (10,240 KiB, 10,485,760 B, 0.00977 GiB) +
ldate3000 +
main imageFile:sd 8cx (front).png +
manufacturerTSMC +
market segmentMobile +
max cpu count1 +
max memory bandwidth29.87 GiB/s (30,586.88 MiB/s, 32.073 GB/s, 32,072.668 MB/s, 0.0292 TiB/s, 0.0321 TB/s) +
max memory channels8 +
microarchitectureCortex-A76 + and Cortex-A55 +
nameSnapdragon 8cx +
process7 nm (0.007 μm, 7.0e-6 mm) +
series800 +
smp max ways1 +
supported memory typeLPDDR4X-4266 +
tdp7 W (7,000 mW, 0.00939 hp, 0.007 kW) +
technologyCMOS +
thread count8 +
word size64 bit (8 octets, 16 nibbles) +