From WikiChip
Difference between revisions of "nec/microarchitectures/sx-aurora"
(initial outline) |
|||
| Line 26: | Line 26: | ||
}} | }} | ||
'''SX-Aurora''' is [[NEC]]'s successor to the {{\\|SX-ACE}}, a [[16 nm]] microarchitecture for [[vector processors]] first introduced in [[2018]]. | '''SX-Aurora''' is [[NEC]]'s successor to the {{\\|SX-ACE}}, a [[16 nm]] microarchitecture for [[vector processors]] first introduced in [[2018]]. | ||
| + | |||
| + | == History == | ||
| + | {{empty section}} | ||
| + | |||
| + | == Architecture == | ||
| + | === Key changes from {{\\|SX-ACE}} === | ||
| + | {{empty section}} | ||
| + | |||
| + | == Block Diagram == | ||
| + | {{empty section}} | ||
| + | |||
| + | == Memory Hierarchy == | ||
| + | {{empty section}} | ||
| + | |||
| + | === Overview == | ||
| + | {{empty section}} | ||
| + | |||
| + | == Vector engine (VE) card == | ||
| + | {{empty section}} | ||
| + | |||
| + | == Die == | ||
| + | {{empty section}} | ||
| + | |||
| + | == Bibliography == | ||
| + | * {{hcbib|30}} | ||
| + | * Supercomputing 2018, NEC Aurora Forum | ||
| + | * ''Some information was obtained directly from NEC'' | ||
Revision as of 20:49, 23 November 2018
| Edit Values | |
| SX-Aurora µarch | |
| General Info | |
| Arch Type | VPU |
| Designer | NEC |
| Manufacturer | TSMC |
| Introduction | 2018 |
| Core Configs | 8 |
| Pipeline | |
| Type | Superscalar, Pipelined |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Stages | 8 |
| Decode | 4-way |
| Cache | |
| L1I Cache | 32 KiB/core |
| L1D Cache | 32 KiB/core |
| L2 Cache | 256 KiB/core |
| L3 Cache | 16 MiB/chip |
| Succession | |
SX-Aurora is NEC's successor to the SX-ACE, a 16 nm microarchitecture for vector processors first introduced in 2018.
Contents
History
| This section is empty; you can help add the missing info by editing this page. |
Architecture
Key changes from SX-ACE
| This section is empty; you can help add the missing info by editing this page. |
Block Diagram
| This section is empty; you can help add the missing info by editing this page. |
Memory Hierarchy
| This section is empty; you can help add the missing info by editing this page. |
= Overview
| This section is empty; you can help add the missing info by editing this page. |
Vector engine (VE) card
| This section is empty; you can help add the missing info by editing this page. |
Die
| This section is empty; you can help add the missing info by editing this page. |
Bibliography
- Template:hcbib
- Supercomputing 2018, NEC Aurora Forum
- Some information was obtained directly from NEC
Facts about "SX-Aurora - Microarchitectures - NEC"
| codename | SX-Aurora + |
| core count | 8 + |
| designer | NEC + |
| first launched | 2018 + |
| full page name | nec/microarchitectures/sx-aurora + |
| instance of | microarchitecture + |
| manufacturer | TSMC + |
| name | SX-Aurora + |
| pipeline stages | 8 + |