Revision as of 21:36, 4 November 2018

7 Series is a series of high-performance RISC-V IP cores designed by SiFive.

Architecture

Key changes from 5 Series

• Core
  • 8-stage pipeline (from 5-7)
    • 10% higher frequency
  • dual-issue (from single-issue)
  • Memory subsystem
    • 0-cycle load-to-use latency (down from 1 cycle)
    • 2-cycle SRAM access time worst case (down from 5 cycles)
    • Fast I/O Port (FIO Port)

Block Diagram

Cluster

Core

Overview

The 7 Series is based on an improved version of the 5 Series which SiFive claims to provide 60% improvement in CoreMarks/MHz as well as 40% improvement in DMIPS/MHz. Series 7 base design is a cluster of up to 9 cores (8+1). Cores can be a mix of 7 Series cores as well as SiFive other existing cores. Everything in the cluster is cache coherent - including any extended SRAM options as well as any custom accelerator attached to the cores. The cluster can be further scaled up through the use of AMBA or TileLink which allows for up to 64 clusters to be integrated onto a single chip. Multi-chip support is also possible via ChipLink.

Core

7 Series cores are based on a dual-issue in-order pipelined design.

Cluster

The basic cluster comprises up to 9 cores configured as 8+1. The type of cores is fully customizable and may incorporate SiFive previous cores (e.g. the high-efficiency 2 Series cores). All the cores sit on a cache coherent bus.

Cores