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Difference between revisions of "nvidia/tegra/xavier"
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=== GPU ===
 
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Xavier implements a derivative of their {{nvidia|Volta|l=arch]} GPU with a set of finer changes to address the machine earning market. It has eight Volta stream multiprocessors along with their standard 128 KiB of L1 cache and a 512 KiB of shared L2. Compared to Parker, Nvidia claims this GPU has 2.1x the graphics performance. Whereas their desktop parts (e.g., GV100) are a very powerful GPU that is used for training, the GPU here is optimized for inference. The most obvious change is that they added int8 support for lower precision to the CUDA tensor cores and those operate at the full 2x throughput of the FP16 ops. There is also 512 CUDA tensor cores, a number that's comparable to Nvidia's top-end models for machine learning (e.g., the GV100 has 672). All of this yields 22.6 tera-operations (int8) per second.
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Xavier implements a derivative of their {{nvidia|Volta|l=arch}} GPU with a set of finer changes to address the machine earning market. It has eight Volta stream multiprocessors along with their standard 128 KiB of L1 cache and a 512 KiB of shared L2. Compared to Parker, Nvidia claims this GPU has 2.1x the graphics performance. Whereas their desktop parts (e.g., GV100) are a very powerful GPU that is used for training, the GPU here is optimized for inference. The most obvious change is that they added int8 support for lower precision to the CUDA tensor cores and those operate at the full 2x throughput of the FP16 ops. There is also 512 CUDA tensor cores, a number that's comparable to Nvidia's top-end models for machine learning (e.g., the GV100 has 672). All of this yields 22.6 tera-operations (int8) per second.
  
 
=== Accelerators ===
 
=== Accelerators ===

Revision as of 20:45, 2 September 2018

Edit Values
Xavier
xavier soc chip.png
General Info
DesignerNvidia
ManufacturerTSMC
Model NumberTegra194
MarketArtificial Intelligence, Embedded
IntroductionJanuary 8, 2018 (announced)
June, 2018 (launched)
General Specs
FamilyTegra
Microarchitecture
ISAARMv8 (ARM)
MicroarchitectureCarmel, Volta
Process12 nm
Transistors9,000,000,000
TechnologyCMOS
Die350 mm²
Word Size64 bit
Cores8
Threads8
Electrical
TDP30 W
TDP (Typical)20 W

Tegra Xavier is a 64-bit ARM high-performance system on a chip for autonomous machines designed by Nvidia and introduced in 2018. Xavier is incorporated into a number of Nvidia's computers including the Jetson Xavier, Drive Xavier, and the Drive Pegasus.

Overview

Overview (HC 30)

Xavier is an autonomous machine process designed by Nvidia and introduced at CES 2018. Silicon came back in the last week of December 2017 with sampling started in the first quarter of 2018. NVIDIA plans on mass production by the end of the year. NVIDIA reported that the product is a result of $2 billion R&D and 8,000 engineering years. The chip is said to have full redundancy and diversity in its functional blocks.

xavier block.svg

The design targets and architecture started back in 2014. The chip itself comprises an eight-core CPU cluster, GPU, deep learning accelerator, vision accelerator, ISP, and a set of multimedia accelerators. Xavier features a large set of I/O and has been designed for safety and reliability supporting various standards such as Functional safety ISO-26262 and ASIL level C. The CPU cluster is fully cache coherent and the coherency is extended to all the other accelerators on-chip.

Architecture

CPU

Main article: Carmel core

The chip features eight control/management Carmel cores, Nvidia's own custom 64-bit ARM cores. Those cores implement ARMv8.2 with RAS support and safety built-in, including dual-execution mode. All cores are fully cache coherent which is extended to the GPU and all the other accelerators in the chip.

GPU

Main article: Volta

Xavier implements a derivative of their Volta GPU with a set of finer changes to address the machine earning market. It has eight Volta stream multiprocessors along with their standard 128 KiB of L1 cache and a 512 KiB of shared L2. Compared to Parker, Nvidia claims this GPU has 2.1x the graphics performance. Whereas their desktop parts (e.g., GV100) are a very powerful GPU that is used for training, the GPU here is optimized for inference. The most obvious change is that they added int8 support for lower precision to the CUDA tensor cores and those operate at the full 2x throughput of the FP16 ops. There is also 512 CUDA tensor cores, a number that's comparable to Nvidia's top-end models for machine learning (e.g., the GV100 has 672). All of this yields 22.6 tera-operations (int8) per second.

Accelerators

Xavier incorporates a Programmable Vision Accelerator (PVA) for processing computer vision. It is capable of 1.6 TOPS and the ability to do stereo disparity (e.g., processing parallax between two cameras to obtain useful information such as depth), optical flow (e.g., direction and speed of vectors), and image processing. Additionally, since the chip is expected to be connected to a network of cameras (e.g., side, front, inside), the chip is capable of doing real-time encoding for all camera in high dynamic range.

Video Processing
Encode Decode
1.2 GPIX/s 1.8 GPIX/s

The chip has an ISP with native full-range HDR support and tile rendering capable of processing at 1.5 GPIX/s.

Deep Learning Accelerator

The chip incorporates a deep learning accelerator (DLA) that implements a number of specific set of deep learning functions common to many applications. This allows them to read the highest possible energy efficiency for those operations. The DLA has a peak performance of 5 TOPS for 16-bit integers or 10 TOPS for 8-bit integer.

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR4X-4266
Supports ECCYes
Channels8
Width32 bit
Max Bandwidth127.1 GiB/s
130,150.4 MiB/s
136.473 GB/s
136,472.586 MB/s
0.124 TiB/s
0.136 TB/s

I/O

  • 16 CSI channels
    • 109 Gbps total bandwidth
  • 1x gE interface
  • 1x 10gE interface

Die

SoC

  • 9,000,000,000 transistors
  • 350 mm² die size
  • TSMC's 12FFN

nvidia xavier die shot.png


nvidia xavier die shot (annotated).png

GPU

  • ~89.2 mm² silicon area
xavier die volta gpu.png


xavier die volta gpu (annotated).png

CPU

See Carmel § CPU Complex.

PVA

xavier die pva.png
xavier die pva (annotated).png

MM Engine / DLA

  • ~21.75 mm² silicon area
xavier die mm-dl accel.png

Borads

  • Jetson Xavier, front

  • Jetson Xavier, back

Documents

Bibliography

  • IEEE Hot Chips 30 Symposium (HCS) 2018.
Retrieved from "https://en.wikichip.org/w/index.php?title=nvidia/tegra/xavier&oldid=82095"
Facts about "Tegra Xavier - Nvidia"
RDF feed
core count8 +
designerNvidia +
die area350 mm² (0.543 in², 3.5 cm², 350,000,000 µm²) +
familyTegra +
first announcedJanuary 8, 2018 +
first launchedJune 2018 +
full page namenvidia/tegra/xavier +
has ecc memory supporttrue +
instance ofmicroprocessor +
isaARMv8 +
isa familyARM +
ldateJune 2018 +
main imageFile:xavier soc chip.png +
manufacturerTSMC +
market segmentArtificial Intelligence + and Embedded +
max memory bandwidth127.1 GiB/s (130,150.4 MiB/s, 136.473 GB/s, 136,472.586 MB/s, 0.124 TiB/s, 0.136 TB/s) +
max memory channels8 +
microarchitectureCarmel + and Volta +
model numberTegra194 +
nameXavier +
process12 nm (0.012 μm, 1.2e-5 mm) +
supported memory typeLPDDR4X-4266 +
tdp30 W (30,000 mW, 0.0402 hp, 0.03 kW) +
tdp (typical)20 W (20,000 mW, 0.0268 hp, 0.02 kW) +
technologyCMOS +
thread count8 +
transistor count9,000,000,000 +
word size64 bit (8 octets, 16 nibbles) +