Semiconductor & Computer Engineering
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Difference between revisions of "hisilicon/kunpeng/hi1612"
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|l1i break=32x48 KiB | |l1i break=32x48 KiB | ||
|l1i desc=8-way set associative | |l1i desc=8-way set associative | ||
| − | |l1d cache=1 | + | |l1d cache=1 MiB |
|l1d break=32x32 KiB | |l1d break=32x32 KiB | ||
|l1d desc=8-way set associative | |l1d desc=8-way set associative | ||
Revision as of 01:19, 1 August 2018
| Edit Values | |
| Hi1612 | |
| General Info | |
| Designer | HiSilicon, ARM Holdings |
| Manufacturer | TSMC |
| Model Number | Hi1610 |
| Market | Server |
| Introduction | June 4, 2016 (announced) June 4, 2016 (launched) |
| General Specs | |
| Family | Hi16xx |
| Frequency | 2,100 MHz |
| Microarchitecture | |
| ISA | ARMv8 (ARM) |
| Microarchitecture | Cortex-A57 |
| Core Name | Cortex-A57 |
| Process | 16 nm |
| Technology | CMOS |
| Word Size | 64 bit |
| Cores | 32 |
| Threads | 32 |
| Max Memory | 256 GiB |
| Multiprocessing | |
| Max SMP | 2-Way (Multiprocessor) |
Hi1612 is a dotriaconta-core 64-bit ARM server microprocessor introduced by HiSilicon in mid-2016. Fabricated by TSMC on a 16 nm process, this chip incorporates 32 Cortex-A57 cores operating at 2.1 GHz. The 1612 supports up to 256 GiB of quad-channel DDR4-2133 memory.
Cache
- Main article: Cortex-A57 § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options |
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Utilizing devices
- HiSilicon D03
This list is incomplete; you can help by expanding it.
Facts about "Hi1612 - HiSilicon"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Hi1612 - HiSilicon#pcie + |
| base frequency | 2,100 MHz (2.1 GHz, 2,100,000 kHz) + |
| core count | 32 + |
| core name | Cortex-A57 + |
| designer | HiSilicon + and ARM Holdings + |
| family | Hi16xx + |
| first announced | June 4, 2016 + |
| first launched | June 4, 2016 + |
| full page name | hisilicon/kunpeng/hi1612 + |
| has ecc memory support | true + |
| instance of | microprocessor + |
| isa | ARMv8 + |
| isa family | ARM + |
| l1$ size | 2,560 KiB (2,621,440 B, 2.5 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 1,024 KiB (1,048,576 B, 1 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 1,536 KiB (1,572,864 B, 1.5 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
| l3$ description | 16-way set associative + |
| l3$ size | 32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) + |
| ldate | June 4, 2016 + |
| manufacturer | TSMC + |
| market segment | Server + |
| max cpu count | 2 + |
| max memory | 262,144 MiB (268,435,456 KiB, 274,877,906,944 B, 256 GiB, 0.25 TiB) + |
| max memory bandwidth | 63.58 GiB/s (65,105.92 MiB/s, 68.269 GB/s, 68,268.505 MB/s, 0.0621 TiB/s, 0.0683 TB/s) + |
| max memory channels | 4 + |
| microarchitecture | Cortex-A57 + |
| model number | Hi1610 + |
| name | Hi1612 + |
| process | 16 nm (0.016 μm, 1.6e-5 mm) + |
| smp max ways | 2 + |
| supported memory type | DDR4-2133 + |
| technology | CMOS + |
| thread count | 32 + |
| used by | HiSilicon D03 + |
| word size | 64 bit (8 octets, 16 nibbles) + |