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Difference between revisions of "intel/microarchitectures/larrabee"
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| − | '''Larrabee''' ('''LRB''') was an experimental [[graphics processing unit]] [[microarchitecture]] designed by [[Intel]] for [[gpgpu|General-purpose GPU computing]]. | + | '''Larrabee''' ('''LRB''') was an experimental [[graphics processing unit]] [[microarchitecture]] designed by [[Intel]] for [[gpgpu|General-purpose GPU computing]] which built on the earlier {{\\|Polaris|Polaris research chip}}. |
Revision as of 08:36, 10 April 2018
| Edit Values | |
| Larrabee µarch | |
| General Info | |
| Arch Type | GPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | August 12, 2008 |
| Phase-out | 2010 |
| Process | 45 nm, 32 nm |
| Core Configs | 8, 16, 24, 32, 40, 48 |
| Instructions | |
| ISA | x86 |
| Extensions | L1OM |
| Succession | |
Larrabee (LRB) was an experimental graphics processing unit microarchitecture designed by Intel for General-purpose GPU computing which built on the earlier Polaris research chip.
Facts about "Larrabee - Microarchitectures - Intel"
| codename | Larrabee + |
| core count | 8 +, 16 +, 24 +, 32 +, 40 + and 48 + |
| designer | Intel + |
| first launched | August 12, 2008 + |
| full page name | intel/microarchitectures/larrabee + |
| instance of | microarchitecture + |
| instruction set architecture | x86 + |
| manufacturer | Intel + |
| microarchitecture type | GPU + |
| name | Larrabee + |
| phase-out | 2010 + |
| process | 45 nm (0.045 μm, 4.5e-5 mm) + and 32 nm (0.032 μm, 3.2e-5 mm) + |