Semiconductor & Computer Engineering
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Difference between revisions of "zhaoxin/kaixian"
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Revision as of 00:32, 15 January 2018
| KaiXian | |
| Developer | Zhaoxin, VIA Technologies |
| Manufacturer | TSMC, HLMC |
| Type | Microprocessors |
| Introduction | 2016 (announced) 2016 (launch) |
| ISA | x86 |
| µarch | Isaiah, Zhangjiang, WuDaoKou, LuJiaZui |
| Word size | 64 bit 8 octets
16 nibbles |
| Process | 40 nm 0.04 μm , 28 nm4.0e-5 mm 0.028 μm
2.8e-5 mm |
| Technology | CMOS |
| Succession | |
| ← | |
| QuadCore | |
Zhaoxin KaiXian (ZX/KX) is a family of x86 microprocessors developed by Zhaoxin for the Chinese market.
Facts about "KaiXian (ZX/KX) - Zhaoxin"
| designer | Zhaoxin + and VIA Technologies + |
| first announced | 2016 + |
| first launched | 2016 + |
| full page name | zhaoxin/kaixian + |
| instance of | microprocessor family + |
| instruction set architecture | x86 + |
| main designer | Zhaoxin + |
| manufacturer | TSMC + and HLMC + |
| microarchitecture | Isaiah +, Zhangjiang +, WuDaoKou + and LuJiaZui + |
| name | KaiXian + |
| process | 40 nm (0.04 μm, 4.0e-5 mm) + and 28 nm (0.028 μm, 2.8e-5 mm) + |
| technology | CMOS + |
| word size | 64 bit (8 octets, 16 nibbles) + |