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Difference between revisions of "amd/microarchitectures/zen+"
| Line 20: | Line 20: | ||
|decode=4-way | |decode=4-way | ||
|isa=x86-64 | |isa=x86-64 | ||
| + | |extension=MOVBE | ||
| + | |extension 2=MMX | ||
| + | |extension 3=SSE | ||
| + | |extension 4=SSE2 | ||
| + | |extension 5=SSE3 | ||
| + | |extension 6=SSSE3 | ||
| + | |extension 7=SSE4.1 | ||
| + | |extension 8=SSE4.2 | ||
| + | |extension 9=POPCNT | ||
| + | |extension 10=AVX | ||
| + | |extension 11=AVX2 | ||
| + | |extension 12=AES | ||
| + | |extension 13=PCLMUL | ||
| + | |extension 14=RDRND | ||
| + | |extension 15=F16C | ||
| + | |extension 16=BMI | ||
| + | |extension 17=BMI2 | ||
| + | |extension 18=RDSEED | ||
| + | |extension 19=ADCX | ||
| + | |extension 20=PREFETCHW | ||
| + | |extension 21=CLFLUSHOPT | ||
| + | |extension 22=XSAVE | ||
| + | |extension 23=SHA | ||
| + | |extension 24=CLZERO | ||
| + | |l1i=64 KiB | ||
| + | |l1i per=core | ||
| + | |l1i desc=4-way set associative | ||
| + | |l1d=32 KiB | ||
| + | |l1d per=core | ||
| + | |l1d desc=8-way set associative | ||
| + | |l2=512 KiB | ||
| + | |l2 per=core | ||
| + | |l2 desc=8-way set associative | ||
| + | |l3=2 MiB | ||
| + | |l3 per=core | ||
| + | |l3 desc=16-way set associative | ||
|predecessor=Zen | |predecessor=Zen | ||
|predecessor link=amd/microarchitectures/zen | |predecessor link=amd/microarchitectures/zen | ||
| Line 67: | Line 103: | ||
*** Bug fixes | *** Bug fixes | ||
*** OEM related issues resolved (unspecified) | *** OEM related issues resolved (unspecified) | ||
| + | |||
| + | == Sockets/Platform == | ||
| + | {{empty section}} | ||
| + | |||
| + | == References == | ||
| + | * AMD CES Tech Day 2018, Jim Anderson | ||
| + | * AMD CES Tech Day 2018, Lis Su | ||
| + | * AMD CES Tech Day 2018, Mark Papermaster | ||
== Documents == | == Documents == | ||
| − | * [[:File:AMD CES Tech Day 2018 Jim Anderson.pdf|AMD Tech Day 2018]] | + | * [[:File:AMD CES Tech Day 2018 Jim Anderson.pdf|AMD Tech Day 2018, Jim Anderson]] |
| + | * [[:File:AMD CES Tech Day 2018 Lisa Su.pdf|AMD Tech Day 2018, Lis Su]] | ||
| + | * [[:File:AMD CES Tech Day 2018 Mark Papermaster.pdf|AMD Tech Day 2018, Mark Papermaster]] | ||
== See Also == | == See Also == | ||
* AMD {{\\|Zen}} | * AMD {{\\|Zen}} | ||
* Intel {{intel|Tigerlake|l=arch}} | * Intel {{intel|Tigerlake|l=arch}} | ||
Revision as of 02:35, 11 January 2018
| Edit Values | |
| Zen+ µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | AMD |
| Manufacturer | GlobalFoundries |
| Introduction | April 2018 |
| Process | 12 nm |
| Core Configs | 2, 4, 6, 8, 12, 16 |
| Pipeline | |
| Type | Superscalar |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Stages | 19 |
| Decode | 4-way |
| Instructions | |
| ISA | x86-64 |
| Extensions | MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, RDRND, F16C, BMI, BMI2, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SHA, CLZERO |
| Cache | |
| L1I Cache | 64 KiB/core 4-way set associative |
| L1D Cache | 32 KiB/core 8-way set associative |
| L2 Cache | 512 KiB/core 8-way set associative |
| L3 Cache | 2 MiB/core 16-way set associative |
| Succession | |
Zen+ (Zen Plus) is a planned microarchitecture being developed by AMD as a successor to Zen. Zen+ is expected to be succeeded by Zen 2.
Zen+ based processors are sold under the brand Ryzen 2nd Generation.
Contents
History
Zen+ is set to succeed Zen in April of 2018. Zen+ will feature the same core as Zen but will take advantage of the new GlobalFoundries' 12nm process to deliver higher clock speeds and improved power consumption. Zen+ was initially mentioned by AMD's senior fellow and lead architect of Zen, Michael Clark, during Hot Chips 28 in 2016 as part of AMD's continuing commitment in the high-performance computing market.
Codenames
 |
Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
| Core | C/T | Target |
|---|---|---|
| Pinnacle Ridge | Up to 8/16 | Mainstream to high-end desktops & enthusiasts market processors |
| Picasso | 4/8 | Mainstream desktop & mobile processors with GPU |
Release Dates
AMD intends on launching 2nd generation Ryzen in April of 2018. 2nd Generation Ryzen Threadripper and Ryzen PRO processors will launch in the second half of 2018.
Architecture
Serving as a light refresh over Zen, those processors have around ten percent higher base frequency for the same power envelope.
Key changes from Zen
- ~10% higher clock frequency
- 12 nm process (from 14 nm)
- Precision Boost 2 (from Precision Boost)
- Mainstream chipsets (See § Sockets/Platform)
- X370 → X470
- Lower Power
- Bug fixes
- OEM related issues resolved (unspecified)
- X370 → X470
Sockets/Platform
 |
This section is empty; you can help add the missing info by editing this page. |
References
- AMD CES Tech Day 2018, Jim Anderson
- AMD CES Tech Day 2018, Lis Su
- AMD CES Tech Day 2018, Mark Papermaster
Documents
See Also
Facts about "Zen+ - Microarchitectures - AMD"
| codename | Zen+ + |
| core count | 2 +, 4 +, 6 +, 8 +, 12 + and 16 + |
| designer | AMD + |
| first launched | April 2018 + |
| full page name | amd/microarchitectures/zen+ + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | GlobalFoundries + |
| microarchitecture type | CPU + |
| name | Zen+ + |
| pipeline stages | 19 + |
| process | 12 nm (0.012 μm, 1.2e-5 mm) + |