Semiconductor & Computer Engineering
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Difference between revisions of "nervana/microarchitectures/lake crest"
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'''Lake Crest''' is a [[neural processor]] microarchitecture designed by [[Nervana]]. | '''Lake Crest''' is a [[neural processor]] microarchitecture designed by [[Nervana]]. | ||
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| + | == Process Technology == | ||
| + | Lake Crest is fabricated on [[TSMC]]'s [[28 nm process]]. | ||
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| + | == Architecture == | ||
| + | {{empty section}} | ||
Revision as of 01:59, 29 December 2017
| Edit Values | |
| Lake Crest µarch | |
| General Info | |
| Arch Type | NPU |
| Designer | Nervana |
| Manufacturer | TSMC |
| Process | 28 nm |
| Succession | |
Lake Crest is a neural processor microarchitecture designed by Nervana.
Process Technology
Lake Crest is fabricated on TSMC's 28 nm process.
Architecture
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This section is empty; you can help add the missing info by editing this page. |
Facts about "Lake Crest - Microarchitectures - Intel Nervana"
| codename | Lake Crest + |
| designer | Nervana + |
| full page name | nervana/microarchitectures/lake crest + |
| instance of | microarchitecture + |
| manufacturer | TSMC + |
| name | Lake Crest + |
| process | 28 nm (0.028 μm, 2.8e-5 mm) + |