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Difference between revisions of "nervana/microarchitectures/lake crest"
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{{nervana title|Lake Crest|arch}} | {{nervana title|Lake Crest|arch}} | ||
− | {{microarchitecture}} | + | {{microarchitecture |
+ | |atype=NPU | ||
+ | |name=Lake Crest | ||
+ | |designer=Nervana | ||
+ | |manufacturer=TSMC | ||
+ | |process=28 nm | ||
+ | |successor=Springs Crest | ||
+ | |successor link=nervana/microarchitectures/spring crest | ||
+ | }} | ||
'''Lake Crest''' is a [[neural processor]] microarchitecture designed by [[Nervana]]. | '''Lake Crest''' is a [[neural processor]] microarchitecture designed by [[Nervana]]. |
Revision as of 01:52, 29 December 2017
Edit Values | |
Lake Crest µarch | |
General Info | |
Arch Type | NPU |
Designer | Nervana |
Manufacturer | TSMC |
Process | 28 nm |
Succession | |
Lake Crest is a neural processor microarchitecture designed by Nervana.
Facts about "Lake Crest - Microarchitectures - Intel Nervana"
codename | Lake Crest + |
designer | Nervana + |
full page name | nervana/microarchitectures/lake crest + |
instance of | microarchitecture + |
manufacturer | TSMC + |
name | Lake Crest + |
process | 28 nm (0.028 μm, 2.8e-5 mm) + |