Semiconductor & Computer Engineering
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{{dec title|Process Technology History}} | {{dec title|Process Technology History}} | ||
| − | This article details details '''[[DEC]]'s [[ | + | This article details details '''[[DEC]]'s [[semiconductor process technology]]''' history for research and posterity. |
The table below shows the history of DEC's process scaling. Values were taken from various DEC documents including historical presentations and journals, ISSCC papers, and IEDM papers. Note that while a great deal of effort was put into ensuring the accuracy of the values, some numbers vary to a small degree between DEC's own documents and therefore discrepancies may exist. | The table below shows the history of DEC's process scaling. Values were taken from various DEC documents including historical presentations and journals, ISSCC papers, and IEDM papers. Note that while a great deal of effort was put into ensuring the accuracy of the values, some numbers vary to a small degree between DEC's own documents and therefore discrepancies may exist. | ||
Latest revision as of 23:02, 25 December 2017
This article details details DEC's semiconductor process technology history for research and posterity.
The table below shows the history of DEC's process scaling. Values were taken from various DEC documents including historical presentations and journals, ISSCC papers, and IEDM papers. Note that while a great deal of effort was put into ensuring the accuracy of the values, some numbers vary to a small degree between DEC's own documents and therefore discrepancies may exist.
Timeline[edit]
High-performance CMOS process started at Digital's Hudson, Massachusetts foundry in the mid-1980s along with Digital's new CMOS VLSI microprocessor designs. Digital adopted a similar manufacturing strategy to Intel whereby scaling of feature sizes occurs along with their development of new generations of high-performance microprocessors. Digital continued to operate the Hudson fab until 1997.Fab-6 in Hudson, Mass was sold to Intel which consequently upgraded it for $800M to Intel's propiatery 0.18 µm (see Intel's Process). Intel continued to operate the fab until late 2013 when they announced that it will be closing the Hudson Fab due to no longer meeting their requirements such as aging technology.
| Year | Process | Node | MLayers | µarchs | Attributes | |||
|---|---|---|---|---|---|---|---|---|
| 1984 | ZMOS | 3 µm | 2 | V-11, MicroVAX II | Tox | 43 nm | ||
| Lg | 3 µm | |||||||
| 1986 | CMOS-1 | 2 µm | 2 | CVAX | Tox | 30 nm | Masks | 12 |
| Vdd | 5 V | |||||||
| Lg | 2 µm | |||||||
| 1988 | CMOS-2 | 1.5 µm | 2 | CVAX+, Rigel | Tox | 22.5 nm | Masks | 13 |
| Vdd | 5 V | |||||||
| Lg | 1.5 µm | |||||||
| 1990 | CMOS-3 | 1 µm | 2 | Mariah | Tox | 15 nm | Masks | 20 |
| Vdd | 3.3 V | |||||||
| Lg | 1 µm | |||||||
| 1991 | CMOS-4 | 0.75 µm | 3 | Alpha 21064, NVAX | Tox | 10.5 nm | Masks | 21 |
| Vdd | 3.3 V | SRAM | 100 µm² | |||||
| Lg | 0.75 µm | Leff | 0.50 µm | |||||
| 1996 | CMOS-4S | 0.675 µm | 3 | NVAX, NVAX+, SOC | Tox | |||
| Lg | 0.675 µm | |||||||
| 1994 | CMOS-5 | 0.50 µm | 4 | Alpha 21164, NVAX++ | Tox | 9 nm | ||
| Vdd | 3.3 V | |||||||
| Lg | 0.50 µm | Leff | 0.365 µm | |||||
| 1996 | CMOS-6 | 0.35 µm | 4 | Alpha 21264, StrongARM | Tox | 6 nm | ||
| Lg | 0.35 µm | Leff | 0.25 µm | |||||
| 1997 | CMOS-7 | 0.25 µm | 5 | Tox | ||||
| 1997 | Changed ownership to Intel (see Intel's Process) | |||||||
| 2013 | Intel announced that it will be closing the Hudson Fab due to dated technology. | |||||||
Additionally, DEC fabricated on Motorola's ECL process:
| Mosaic1 | 3 µm ECL |
| Mosaic2 | 1 µm ECL |
| Mosaic3 |
Other processes[edit]
Semiconductor Process history by company:
- DEC
- Intel