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Difference between revisions of "intel/microarchitectures/cannon lake"
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{{intel title|Cannonlake|arch}}
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{{intel title|Cannon Lake|arch}}
 
{{microarchitecture
 
{{microarchitecture
 
|atype=CPU
 
|atype=CPU
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|name=Cannonlake
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|name=Cannon Lake
 
|designer=Intel
 
|designer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
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|isa=x86-64
 
|isa=x86-64
  
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|core name=Cannonlake Y
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|core name=Cannon Lake Y
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|core name 2=Cannonlake U
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|core name 2=Cannon Lake U
 
|predecessor=Kaby Lake
 
|predecessor=Kaby Lake
 
|predecessor link=intel/microarchitectures/kaby lake
 
|predecessor link=intel/microarchitectures/kaby lake
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|succession=Yes
 
|succession=Yes
 
}}
 
}}
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'''Cannonlake''' ('''CNL''') (formerly '''Skymont''') is a planned [[microarchitecture]] by [[Intel]] as a successor to {{\\|Kaby Lake}}. Cannonlake is expected to be fabricated using a [[10 nm process]] and is set to be introduced in the fourth quarter of [[2017]]. Cannonlake is the "Process" microarchitecture as part of Intel's {{intel|PAO}} model.
+
'''Cannon Lake''' ('''CNL''') (formerly '''Skymont''') is a planned [[microarchitecture]] by [[Intel]] as a successor to {{\\|Kaby Lake}}. Cannon Lake is expected to be fabricated using a [[10 nm process]] and is set to be introduced in the fourth quarter of [[2017]]. Cannon Lake is the "Process" microarchitecture as part of Intel's {{intel|PAO}} model.
  
−
For mobile, Cannonlake is expected to be branded as 8th Generation Intel {{intel|Core i3}}, {{intel|Core i5}}. and {{intel|Core i7}} processors.
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For mobile, Cannon Lake is expected to be branded as 8th Generation Intel {{intel|Core i3}}, {{intel|Core i5}}. and {{intel|Core i7}} processors.
  
 
== Process Technology ==
 
== Process Technology ==
−
Cannonlake is manufactured on Intel's [[10 nm process]] (P1274). Intel's 10 nm process is the first high-volume manufacturing process to employ [[Self-Aligned Quad Patterning]] (SAQP) (goes under the "Hyper-Scaling" marketing name). Intel's 10nm features a 0.0367 µm² [[SRAM]] bit cell.
+
Cannon Lake is manufactured on Intel's [[10 nm process]] (P1274). Intel's 10 nm process is the first high-volume manufacturing process to employ [[Self-Aligned Quad Patterning]] (SAQP) (goes under the "Hyper-Scaling" marketing name). Intel's 10nm features a 0.0367 µm² [[SRAM]] bit cell.
  
 
[[Scaling]]:
 
[[Scaling]]:
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{| class="wikitable"
 
{| class="wikitable"
 
|-
 
|-
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! !! Broadwell !! Cannonlake !! Δ !! rowspan="8" | [[File:intel 10nm fin.png|250px]]
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! !! Broadwell !! Cannon Lake !! Δ !! rowspan="8" | [[File:intel 10nm fin.png|250px]]
 
|-
 
|-
 
| || [[14 nm]] || [[10 nm]] ||
 
| || [[14 nm]] || [[10 nm]] ||
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! Core !! Abbrev !! Description !! Graphics !! Target
 
! Core !! Abbrev !! Description !! Graphics !! Target
 
|-
 
|-
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| {{intel|Cannonlake Y|l=core}} || CNL-Y || Extremely low power || GT2 || 2-in-1s detachable, tablets, and computer sticks
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| {{intel|Cannon Lake Y|l=core}} || CNL-Y || Extremely low power || GT2 || 2-in-1s detachable, tablets, and computer sticks
 
|-
 
|-
−
| {{intel|Cannonlake U|l=core}} || CNL-U || Ultra-low Power || GT2/GT3 || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room
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| {{intel|Cannon Lake U|l=core}} || CNL-U || Ultra-low Power || GT2/GT3 || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room
 
|-
 
|-
−
| {{intel|Cannonlake H|l=core}} || CNL-H || High-performance Graphics || GT2/GT3 || Ultimate mobile performance, mobile workstations
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| {{intel|Cannon Lake H|l=core}} || CNL-H || High-performance Graphics || GT2/GT3 || Ultimate mobile performance, mobile workstations
 
|-  
 
|-  
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| {{intel|Cannonlake S|l=core}} || CNL-S || Performance-optimized lifestyle || GT2/GT3 || Desktop performance to value, AiOs, and minis
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| {{intel|Cannon Lake S|l=core}} || CNL-S || Performance-optimized lifestyle || GT2/GT3 || Desktop performance to value, AiOs, and minis
 
|-  
 
|-  
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| {{intel|Cannonlake DT|l=core}} || CNL-DT || Workstation || GT2 || Workstations & entry-level servers
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| {{intel|Cannon Lake DT|l=core}} || CNL-DT || Workstation || GT2 || Workstations & entry-level servers
 
|}
 
|}
  
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** {{intel|Iris Plus Graphics 650}} '''→''' {{intel|Iris Plus Graphics 750}} (unknown change)
 
** {{intel|Iris Plus Graphics 650}} '''→''' {{intel|Iris Plus Graphics 750}} (unknown change)
  
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== All Cannonlake Chips ==
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== All Cannon Lake Chips ==
 
<!-- NOTE:  
 
<!-- NOTE:  
 
           This table is generated automatically from the data in the actual articles.
 
           This table is generated automatically from the data in the actual articles.
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{{comp table start}}
 
{{comp table start}}
 
<table class="comptable sortable tc18 tc19 tc20 tc21 tc22 tc23">
 
<table class="comptable sortable tc18 tc19 tc20 tc21 tc22 tc23">
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<tr class="comptable-header"><th>&nbsp;</th><th colspan="23">Cannonlake Chips</th></tr>
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<tr class="comptable-header"><th>&nbsp;</th><th colspan="23">Cannon Lake Chips</th></tr>
 
<tr class="comptable-header"><th>&nbsp;</th><th colspan="13">Main processor</th><th colspan="3">IGP</th><th colspan="7">Major Feature Diff</th></tr>
 
<tr class="comptable-header"><th>&nbsp;</th><th colspan="13">Main processor</th><th colspan="3">IGP</th><th colspan="7">Major Feature Diff</th></tr>
 
<tr class="comptable-header"><th class="unsortable">Model</th><th>Launched</th><th>Price</th><th>Family</th><th>Platform</th><th>Core</th><th>C</th><th>T</th><th>L3$</th><th>L4$</th><th>TDP</th><th>Freq</th><th>Turbo</th><th>Max Mem</th><th>Name</th><th>Freq</th><th>Turbo</th><th>{{intel|turbo boost|TBT}}</th><th>HT</th><th>AVX2</th><th>TXT</th><th>TSX</th><th>vPro</th><th>VT-d</th></tr>
 
<tr class="comptable-header"><th class="unsortable">Model</th><th>Launched</th><th>Price</th><th>Family</th><th>Platform</th><th>Core</th><th>C</th><th>T</th><th>L3$</th><th>L4$</th><th>TDP</th><th>Freq</th><th>Turbo</th><th>Max Mem</th><th>Name</th><th>Freq</th><th>Turbo</th><th>{{intel|turbo boost|TBT}}</th><th>HT</th><th>AVX2</th><th>TXT</th><th>TSX</th><th>vPro</th><th>VT-d</th></tr>
 
<tr class="comptable-header comptable-header-sep"><th>&nbsp;</th><th colspan="23">[[Uniprocessors]]</th></tr>
 
<tr class="comptable-header comptable-header-sep"><th>&nbsp;</th><th colspan="23">[[Uniprocessors]]</th></tr>
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{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Cannonlake]] [[max cpu count::1]]
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{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Cannon Lake]] [[max cpu count::1]]
 
  |?full page name
 
  |?full page name
 
  |?model number
 
  |?model number
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  |limit=100
 
}}
 
}}
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<tr><th>&nbsp;</th><th colspan="23"><span style="font-size: 20px;">No Cannonlake Chips have been released yet.</span></th></tr>
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<tr><th>&nbsp;</th><th colspan="23"><span style="font-size: 20px;">No Cannon Lake Chips have been released yet.</span></th></tr>
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{{comp table count|ask=[[Category:microprocessor models by intel]][[instance of::microprocessor]][[microarchitecture::Cannonlake]]}}
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{{comp table count|ask=[[Category:microprocessor models by intel]][[instance of::microprocessor]][[microarchitecture::Cannon Lake]]}}
 
</table>
 
</table>
 
{{comp table end}}
 
{{comp table end}}

Revision as of 00:34, 13 December 2017

Edit Values
Cannon Lake µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
Introduction2017
Process10 nm
Instructions
ISAx86-64
Cores
Core NamesCannon Lake Y,
Cannon Lake U
Succession

Cannon Lake (CNL) (formerly Skymont) is a planned microarchitecture by Intel as a successor to Kaby Lake. Cannon Lake is expected to be fabricated using a 10 nm process and is set to be introduced in the fourth quarter of 2017. Cannon Lake is the "Process" microarchitecture as part of Intel's PAO model.

For mobile, Cannon Lake is expected to be branded as 8th Generation Intel Core i3, Core i5. and Core i7 processors.

Process Technology

Cannon Lake is manufactured on Intel's 10 nm process (P1274). Intel's 10 nm process is the first high-volume manufacturing process to employ Self-Aligned Quad Patterning (SAQP) (goes under the "Hyper-Scaling" marketing name). Intel's 10nm features a 0.0367 µm² SRAM bit cell.

Scaling:

Broadwell Cannon Lake Δ intel 10nm fin.png
14 nm 10 nm
Fin Pitch 42 nm 34 0.81x
Fin Width​ 8 nm  ? nm  ?x
Fin Height​ 42 nm 53 nm 1.24x
Gate Pitch 70 nm 54 nm 0.77x
Interconnect Pitch 52 nm 36 nm 0.69x
Cell Height 399 nm 272 nm 0.68x

Codenames

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.
Core Abbrev Description Graphics Target
Cannon Lake Y CNL-Y Extremely low power GT2 2-in-1s detachable, tablets, and computer sticks
Cannon Lake U CNL-U Ultra-low Power GT2/GT3 Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room
Cannon Lake H CNL-H High-performance Graphics GT2/GT3 Ultimate mobile performance, mobile workstations
Cannon Lake S CNL-S Performance-optimized lifestyle GT2/GT3 Desktop performance to value, AiOs, and minis
Cannon Lake DT CNL-DT Workstation GT2 Workstations & entry-level servers

Architecture

New text document.svg This section is empty; you can help add the missing info by editing this page.

Key changes from Kaby Lake

  • 10 nm process (from 14 nm)
  • Mainstream chipset
    • 200 Series chipset → 300 Series chipset
      • Integrated Programmable (Open FW SDK) Quad-Core Audio DSP
      • Soundwire Digital Audio Interface
      • Integrated USB 3.1 (10 Gib/s)
        • Up to 6 ports
      • Integrated Intel wireless controller (IEEE 802.11ac)
      • Integrated SDXC 3.0 controller
      • Thunderbolt 3.0(Titan Ridge) with DisplayPort 1.4 support
      • C10 & S0ix Support for Modern Standby

All Cannon Lake Chips

 Cannon Lake Chips
 Main processorIGPMajor Feature Diff
ModelLaunchedPriceFamilyPlatformCoreCTL3$L4$TDPFreqTurboMax MemNameFreqTurboTBTHTAVX2TXTTSXvProVT-d
 Uniprocessors
M3-8114YCore M3Cannon Lake Y241.5 GHz
1,500 MHz
1,500,000 kHz
16 GiB
16,384 MiB
16,777,216 KiB
17,179,869,184 B
0.0156 TiB
UHD Graphics ?300 MHz
0.3 GHz
300,000 KHz
✔✔✔✘✘✘✔
i3-8121U15 May 2018Core i3Cannon Lake U244 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
15 W
15,000 mW
0.0201 hp
0.015 kW
2.2 GHz
2,200 MHz
2,200,000 kHz
3.2 GHz
3,200 MHz
3,200,000 kHz
32 GiB
32,768 MiB
33,554,432 KiB
34,359,738,368 B
0.0313 TiB
✔✔✔✘✘✘✔
 No Cannon Lake Chips have been released yet.
Count: 2

References

  • Mark Bohr, Intel. Intel Technology and Manufacturing Day. Mar 28, 2017.

See also

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/cannon_lake&oldid=69163"
Facts about "Cannon Lake - Microarchitectures - Intel"
RDF feed
codenameCannonlake +
designerIntel +
first launched2017 +
full page nameintel/microarchitectures/cannon lake +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameCannonlake +
process10 nm (0.01 μm, 1.0e-5 mm) +