Difference between revisions of "nxp/qoriq"

Revision as of 22:58, 24 October 2017

QorIQ

Developer	Freescale, NXP
Manufacturer	IBM, TSMC
Type	System on Chips
Introduction	June 16, 2008 (announced) June 16, 2008 (launch)
Architecture	POWER & ARM Communication SoC
Word size	32 bit 4 octets 8 nibbles , 64 bit 8 octets 16 nibbles
Process	45 nm 0.045 μm 4.5e-5 mm , 32 nm 0.032 μm 3.2e-5 mm , 20 nm 0.02 μm 2.0e-5 mm , 16 nm 0.016 μm 1.6e-5 mm
Technology	CMOS
Clock	533 MHz-2,000 MHz
Succession
←
PowerQUICC

QorIQ (pronounced "Core IQ") is a family of ARM and POWER embedded and networking microprocessors designed and sold by NXP (formerly Freescale) since 2008 as a successor to the PowerQUICC family.

Overview

Introduced in 2008 by Freescale as a successor to the PowerQUICC family, then one of industry's most popular communications processors. Like the PowerQUICC brand, QorIQ spanned the entire range of products from low-power and low-cost to large multi-core designs. Original designs were based on the POWER architecture. In 2012 Freescale announced the Layerscape series that adopts the ARM architecture which Freescale/NXP has been using since.

Identification

Only applies to original QorIQ P & T series:

Identification

QorIQ

P

4

08

0

QorIQ

P

1

01

3

Iteration/Version

Core Count

01	single-core
02	dual-core
04	quad-core
08	octa-core

Platform Level

Technology Node

P	45 nm process
T	28 nm process

Brand Name

QorIQ

Series

This section requires expansion; you can help adding the missing info.

P Series

Announced in mid-2008, the QorIQ P-series are POWER-based microprocessors based on the e500 microarchitecture. Being the first Freescale multicore networking applications based on the 45 nm process, those parts offered a migration path for PowerQUICC II Pro and PowerQUICC III processor customers. All chips are fully software compatible with each other and existing PowerQUICC processors with multi-core parts supporting both symmetric and asymmetric multiprocessing.

P1

The P1 series are designed for low-power fan-less design designed to succeed previous models (e.g., PowerQUICC II Pro) with higher performance at the same power envelope. P1 parts are designed for the applications such as Ethernet switch controllers, gateways, wireless LAN access points, network printing/storage, and other networking devices with tight thermal constraints.

	List of QorIQ P1 Processors
Model	Launched	Cores	Frequency	L2$	Max Power
P1010	2009	1	667 MHz 0.667 GHz 667,000 kHz 800 MHz 0.8 GHz 800,000 kHz		1.6 W 1,600 mW 0.00215 hp 0.0016 kW
P1011	2009	1	800 MHz 0.8 GHz 800,000 kHz	256 KiB 0.25 MiB 262,144 B 2.441406e-4 GiB	1.56 W 1,560 mW 0.00209 hp 0.00156 kW
P1012	January 2010	1	533 MHz 0.533 GHz 533,000 kHz 800 MHz 0.8 GHz 800,000 kHz	256 KiB 0.25 MiB 262,144 B 2.441406e-4 GiB	1.6 W 1,600 mW 0.00215 hp 0.0016 kW
P1013	2010	1	1,067 MHz 1.067 GHz 1,067,000 kHz	256 KiB 0.25 MiB 262,144 B 2.441406e-4 GiB	3 W 3,000 mW 0.00402 hp 0.003 kW
P1014	2011	1	800 MHz 0.8 GHz 800,000 kHz	256 KiB 0.25 MiB 262,144 B 2.441406e-4 GiB	1.13 W 1,130 mW 0.00152 hp 0.00113 kW
P1015	2012	1	400 MHz 0.4 GHz 400,000 kHz 533 MHz 0.533 GHz 533,000 kHz	256 KiB 0.25 MiB 262,144 B 2.441406e-4 GiB	1.4 W 1,400 mW 0.00188 hp 0.0014 kW
P1016		1			1.53 W 1,530 mW 0.00205 hp 0.00153 kW
P1017		1			2 W 2,000 mW 0.00268 hp 0.002 kW
P1020	2009	2	800 MHz 0.8 GHz 800,000 kHz	256 KiB 0.25 MiB 262,144 B 2.441406e-4 GiB	1.89 W 1,890 mW 0.00253 hp 0.00189 kW
P1021	January 2010	2	1,200 MHz 1.2 GHz 1,200,000 kHz	256 KiB 0.25 MiB 262,144 B 2.441406e-4 GiB	4.5 W 4,500 mW 0.00603 hp 0.0045 kW
P1022	2010	2	1,067 MHz 1.067 GHz 1,067,000 kHz	256 KiB 0.25 MiB 262,144 B 2.441406e-4 GiB	2.5 W 2,500 mW 0.00335 hp 0.0025 kW
P1023		2			2 W 2,000 mW 0.00268 hp 0.002 kW
P1024	2012	2	533 MHz 0.533 GHz 533,000 kHz	256 KiB 0.25 MiB 262,144 B 2.441406e-4 GiB	1.6 W 1,600 mW 0.00215 hp 0.0016 kW
P1025		2			1.69 W 1,690 mW 0.00227 hp 0.00169 kW
Count: 14

P2

The P2 series are designed to succeed the PowerQUICC III parts. These parts feature a large cache that may be configured as stashing memory, four Ethernet controllers with QoS features and flow control, DDR2/DDR3 SDRAM Controller with ECC support, four general purpose SerDes lanes that may be configured as either two Serial RapidIO ports, three PCI Express ports and two SGMII ports.

	List of QorIQ P2 Processors
Model	Launched	Cores	Frequency	L2$	Max Power
P2010	2009	1	1,200 MHz 1.2 GHz 1,200,000 kHz 800 MHz 0.8 GHz 800,000 kHz 1,000 MHz 1 GHz 1,000,000 kHz 1,333 MHz 1.333 GHz 1,333,000 kHz	512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB	6.7 W 6,700 mW 0.00898 hp 0.0067 kW
P2020	2009	2	800 MHz 0.8 GHz 800,000 kHz 1,200 MHz 1.2 GHz 1,200,000 kHz 1,333 MHz 1.333 GHz 1,333,000 kHz	512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB	8 W 8,000 mW 0.0107 hp 0.008 kW
Count: 2

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 <table class="comptable sortable tc4">
 {{comp table header|main|5:List of QorIQ P1 Processors}}
-{{comp table header|cols|Launched|Cores|%Frequency|L2$}}
+{{comp table header|cols|Launched|Cores|%Frequency|L2$|Max Power}}
 {{#ask: [[Category:microprocessor models by freescale]] [[family::QorIQ]] [[series::P1]]
   |?full page name
@@ Line 96: / Line 96: @@
   |?base frequency#MHz
   |?l2$ size#KiB
+ |?power dissipation#W
   |format=template
   |template=proc table 3
-  |userparam=6
+  |userparam=7
   |mainlabel=-
 }}
@@ Line 118: / Line 119: @@
 <table class="comptable sortable tc4">
 {{comp table header|main|5:List of QorIQ P2 Processors}}
-{{comp table header|cols|Launched|Cores|%Frequency|L2$}}
+{{comp table header|cols|Launched|Cores|%Frequency|L2$|Max Power}}
 {{#ask: [[Category:microprocessor models by freescale]] [[family::QorIQ]] [[series::P2]]
   |?full page name
@@ Line 126: / Line 127: @@
   |?base frequency#MHz
   |?l2$ size#KiB
+ |?power dissipation#W
   |format=template
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-  |userparam=6
+  |userparam=7
   |mainlabel=-
 }}

designer	Freescale + and NXP +
first announced	June 16, 2008 +
first launched	June 16, 2008 +
full page name	nxp/qoriq +
instance of	system on a chip family +
main designer	Freescale +
manufacturer	TSMC + and IBM +
name	QorIQ +
process	45 nm (0.045 μm, 4.5e-5 mm) +, 32 nm (0.032 μm, 3.2e-5 mm) +, 20 nm (0.02 μm, 2.0e-5 mm) + and 16 nm (0.016 μm, 1.6e-5 mm) +
technology	CMOS +
word size	32 bit (4 octets, 8 nibbles) + and 64 bit (8 octets, 16 nibbles) +

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Revision as of 22:58, 24 October 2017

Contents

Overview

Identification

Series

P Series

P1

P2

See also