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==== P2 ====
 
==== P2 ====
 
The P2 series are designed to succeed the PowerQUICC III parts. These parts feature a large cache that may be configured as stashing memory, four Ethernet controllers with QoS features and flow control, DDR2/DDR3 SDRAM Controller with ECC support, four general purpose SerDes lanes that may be configured as either two Serial RapidIO ports, three PCI Express ports and two SGMII ports.
 
The P2 series are designed to succeed the PowerQUICC III parts. These parts feature a large cache that may be configured as stashing memory, four Ethernet controllers with QoS features and flow control, DDR2/DDR3 SDRAM Controller with ECC support, four general purpose SerDes lanes that may be configured as either two Serial RapidIO ports, three PCI Express ports and two SGMII ports.
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{{comp table start}}
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<table class="comptable sortable tc4">
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{{comp table header|main|5:List of QorIQ P2 Processors}}
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{{comp table header|cols|Launched|Cores|%Frequency|L2$}}
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{{#ask: [[Category:microprocessor models by freescale]] [[family::QorIQ]] [[series::P2]]
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== See also ==
 
== See also ==
 
* [[Cavium]] {{cavium|ThunderX}}
 
* [[Cavium]] {{cavium|ThunderX}}
 
* [[Intel]] {{intel|Atom}}
 
* [[Intel]] {{intel|Atom}}

Revision as of 21:27, 24 October 2017

QorIQ
Developer Freescale, NXP
Manufacturer IBM, TSMC
Type System on Chips
Introduction June 16, 2008 (announced)
June 16, 2008 (launch)
Architecture POWER & ARM Communication SoC
Word size 32 bit
4 octets
8 nibbles
, 64 bit
8 octets
16 nibbles
Process 45 nm
0.045 μm
4.5e-5 mm
, 32 nm
0.032 μm
3.2e-5 mm
, 20 nm
0.02 μm
2.0e-5 mm
, 16 nm
0.016 μm
1.6e-5 mm
Technology CMOS
Clock 533 MHz-2,000 MHz
Succession
←
PowerQUICC

QorIQ (pronounced "Core IQ") is a family of ARM and POWER embedded and networking microprocessors designed and sold by NXP (formerly Freescale) since 2008 as a successor to the PowerQUICC family.

Overview

Introduced in 2008 by Freescale as a successor to the PowerQUICC family, then one of industry's most popular communications processors. Like the PowerQUICC brand, QorIQ spanned the entire range of products from low-power and low-cost to large multi-core designs. Original designs were based on the POWER architecture. In 2012 Freescale announced the Layerscape series that adopts the ARM architecture which Freescale/NXP has been using since.

Identification

Only applies to original QorIQ P & T series:

Identification
QorIQ  P4080 
QorIQ  P1013 
      Iteration/Version
     Core Count
01single-core
02dual-core
04quad-core
08octa-core
    Platform Level
   Technology Node
P45 nm process
T28 nm process
  
 Brand Name
QorIQ

Series

New text document.svg This section requires expansion; you can help adding the missing info.

P Series

QorIQ platform levels.png

Announced in mid-2008, the QorIQ P-series are POWER-based microprocessors based on the e500 microarchitecture. Being the first Freescale multicore networking applications based on the 45 nm process, those parts offered a migration path for PowerQUICC II Pro and PowerQUICC III processor customers. All chips are fully software compatible with each other and existing PowerQUICC processors with multi-core parts supporting both symmetric and asymmetric multiprocessing.

P1

The P1 series are designed for low-power fan-less design designed to succeed previous models (e.g., PowerQUICC II Pro) with higher performance at the same power envelope. P1 parts are designed for the applications such as Ethernet switch controllers, gateways, wireless LAN access points, network printing/storage, and other networking devices with tight thermal constraints.

 List of QorIQ P1 Processors
ModelLaunchedCoresFrequencyL2$
P101020091667 MHz
0.667 GHz
667,000 kHz
800 MHz
0.8 GHz
800,000 kHz
P101120091800 MHz
0.8 GHz
800,000 kHz
256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
P1012January 20101533 MHz
0.533 GHz
533,000 kHz
800 MHz
0.8 GHz
800,000 kHz
256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
P1013201011,067 MHz
1.067 GHz
1,067,000 kHz
256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
P101420111800 MHz
0.8 GHz
800,000 kHz
256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
P101520121400 MHz
0.4 GHz
400,000 kHz
533 MHz
0.533 GHz
533,000 kHz
256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
P10161
P10171
P102020092800 MHz
0.8 GHz
800,000 kHz
256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
P1021January 201021,200 MHz
1.2 GHz
1,200,000 kHz
256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
P1022201021,067 MHz
1.067 GHz
1,067,000 kHz
256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
P10232
P102420122533 MHz
0.533 GHz
533,000 kHz
256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
P10252
Count: 14

P2

The P2 series are designed to succeed the PowerQUICC III parts. These parts feature a large cache that may be configured as stashing memory, four Ethernet controllers with QoS features and flow control, DDR2/DDR3 SDRAM Controller with ECC support, four general purpose SerDes lanes that may be configured as either two Serial RapidIO ports, three PCI Express ports and two SGMII ports.

 List of QorIQ P2 Processors
ModelLaunchedCoresFrequencyL2$
P2010200911,200 MHz
1.2 GHz
1,200,000 kHz
800 MHz
0.8 GHz
800,000 kHz
1,000 MHz
1 GHz
1,000,000 kHz
1,333 MHz
1.333 GHz
1,333,000 kHz
512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
P202020092800 MHz
0.8 GHz
800,000 kHz
1,200 MHz
1.2 GHz
1,200,000 kHz
1,333 MHz
1.333 GHz
1,333,000 kHz
512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
Count: 2

See also

Retrieved from "https://en.wikichip.org/w/index.php?title=nxp/qoriq&oldid=66216"
Facts about "QorIQ - NXP"
RDF feed
designerFreescale + and NXP +
first announcedJune 16, 2008 +
first launchedJune 16, 2008 +
full page namenxp/qoriq +
instance ofsystem on a chip family +
main designerFreescale +
manufacturerTSMC + and IBM +
nameQorIQ +
process45 nm (0.045 μm, 4.5e-5 mm) +, 32 nm (0.032 μm, 3.2e-5 mm) +, 20 nm (0.02 μm, 2.0e-5 mm) + and 16 nm (0.016 μm, 1.6e-5 mm) +
technologyCMOS +
word size32 bit (4 octets, 8 nibbles) + and 64 bit (8 octets, 16 nibbles) +