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Difference between revisions of "intel/microarchitectures/goldmont plus"
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(https://patchwork.kernel.org/patch/9836747/ "Goldmont Plus has 4-wide pipeline for Topdown")
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== Architecture ==
 
== Architecture ==
 
=== Key changes from {{\\|Goldmont}} ===
 
=== Key changes from {{\\|Goldmont}} ===
* 4-way decode (from 3-way)
+
* 4-way decode (from 3-way)<ref>https://patchwork.kernel.org/patch/9836747/</ref>
  
 
=== Block Diagram ===
 
=== Block Diagram ===

Revision as of 03:04, 26 July 2017

Edit Values
Goldmont Plus µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
Process14 nm
Core Configs2, 4, 8
Pipeline
TypeSuperscalar
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages12-14
Instructions
ISAIA-32, x86-64
ExtensionsMOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, SHA
Cache
L1I Cache32 KiB/Core
8-way set associative
L1D Cache24 KiB/Core
6-way set associative
L2 Cache1 MiB/2 Cores
16-way set associative
Cores
Core NamesGemini Lake
Succession

Goldmont Plus is Intel's 14 nm microarchitecture of system on chips for the ultra-low power (ULP) devices serving as a successor to Goldmont. Goldmont Plus-based processors and SoCs are part of the Atom, Pentium, and Celeron families.

Codenames

Platform Core Target
Gemini Lake Gemini Lake Tablets, Entry-level PCs

Architecture

Key changes from Goldmont

  • 4-way decode (from 3-way)[1]

Block Diagram

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Core

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  1. https://patchwork.kernel.org/patch/9836747/
codenameGoldmont Plus +
core count2 +, 4 + and 8 +
designerIntel +
full page nameintel/microarchitectures/goldmont plus +
instance ofmicroarchitecture +
instruction set architectureIA-32 + and x86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameGoldmont Plus +
pipeline stages (max)14 +
pipeline stages (min)12 +
process14 nm (0.014 μm, 1.4e-5 mm) +