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Difference between revisions of "acorn/microarchitectures/arm3"
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+ | |l1 desc=64-way set associative | ||
|predecessor=ARM2 | |predecessor=ARM2 | ||
|predecessor link=arm holdings/microarchitectures/arm2 | |predecessor link=arm holdings/microarchitectures/arm2 |
Revision as of 16:24, 28 June 2017
Edit Values | |
ARM3 µarch | |
General Info | |
Arch Type | CPU |
Designer | ARM Holdings |
Manufacturer | VLSI Technology, Sanyo |
Introduction | 1989 |
Process | 1.5 µm |
Core Configs | 1 |
Pipeline | |
Type | Scalar, Pipelined |
Stages | 3 |
Decode | 1-way |
Instructions | |
ISA | ARMv2a |
Cache | |
L1 Cache | 4 KiB/core 64-way set associative |
Succession | |
ARM3 is the second-generation commercial ARM implementation designed by ARM Holdings (then Acorn Computers) as a successor to the ARM2.
Contents
Overview
The ARM3 builds on the ARM2 with higher performance through the introduction of on-die cache but without any major changes to the core itself. The ARM3 can operate at up to 25 MHz with a peak performance of 25 MIPS and a sustainable performance of 12 MIPS.
Process Technology
- See also: 1.5 µm process
The ARM3 was implemented on a 1.5 µm double-level metal CMOS process.
Architecture
Key changes from ARM2
- Goal 3x the performance
New instructions
New ARM3 instructions:
Memory:
-
SWP
- Swap word memory-register, Atomic (uninterruptible)
Die
- 12 MHz, 1 W
- 1.5 µm DLM CMOS
- 8.72 mm x 9.95 mm
- 86.764 mm² die size
- 309,656 transistors
- 206,454 SRAM
- 62,973 CAM
- 40,229 logic
- QFP-160
- 119 signal pins
- 41 power/ground pins
All ARM2 Chips
This section is empty; you can help add the missing info by editing this page. |
References
- Thomas, A. R. P., et al. "A 2nd Generation 32b RISC Processor with 4KByte Cache." Solid-State Circuits Conference, 1989. ESSCIRC'89. Proceedings of the 15th European. IEEE, 1989.
Facts about "ARM3 - Microarchitectures - Acorn"
codename | ARM3 + |
core count | 1 + |
designer | ARM Holdings + |
first launched | 1989 + |
full page name | acorn/microarchitectures/arm3 + |
instance of | microarchitecture + |
instruction set architecture | ARMv2a + |
manufacturer | VLSI Technology + and Sanyo + |
microarchitecture type | CPU + |
name | ARM3 + |
pipeline stages | 3 + |
process | 1,500 nm (1.5 μm, 0.0015 mm) + |