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Difference between revisions of "acorn/microarchitectures/arm3"
< acorn
(Created page with "{{armh title|ARM3|arch}} {{microarchitecture |atype=CPU |name=ARM3 |designer=ARM Holdings |manufacturer=VLSI Technology |manufacturer 2=Sanyo |introduction=1989 |process=1.5...") |
(No difference)
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Revision as of 13:01, 28 June 2017
Edit Values | |
ARM3 µarch | |
General Info | |
Arch Type | CPU |
Designer | ARM Holdings |
Manufacturer | VLSI Technology, Sanyo |
Introduction | 1989 |
Process | 1.5 µm |
Core Configs | 1 |
Pipeline | |
Type | Scalar, Pipelined |
Stages | 3 |
Decode | 1-way |
Instructions | |
ISA | ARMv2 |
Succession | |
ARM3 is the second-generation commercial ARM implementation designed by ARM Holdings (then Acorn Computers) as a successor to the ARM2.
Retrieved from "https://en.wikichip.org/w/index.php?title=acorn/microarchitectures/arm3&oldid=48530"
Facts about "ARM3 - Microarchitectures - Acorn"
codename | ARM3 + |
core count | 1 + |
designer | ARM Holdings + |
first launched | 1989 + |
full page name | acorn/microarchitectures/arm3 + |
instance of | microarchitecture + |
instruction set architecture | ARMv2 + |
manufacturer | VLSI Technology + and Sanyo + |
microarchitecture type | CPU + |
name | ARM3 + |
pipeline stages | 3 + |
process | 1,500 nm (1.5 μm, 0.0015 mm) + |