Revision as of 14:45, 15 January 2017

Skylake (SKL) is Intel's successor to Broadwell, a 14 nm process microarchitecture for mainstream desktops, servers, and mobile devices. Skylake succeeded the short-lived Broadwell which experienced severe delays. Skylake is the "Architecture" phase as part of Intel's PAO model. The microarchitecture was developed by Intel's R&D center in Haifa, Israel.

For desktop and mobile, Skylake is branded as 6th Generation Intel Core i3, Core i5. and Core i7 processors. For server class processors, Intel branded it as Xeon E3 v6, Xeon E5 v6, and Xeon E7 v6.

Codenames

Process Technology

Main article: Broadwell § Process Technology

Skylake uses the same 14 nm process used for the Broadwell microarchitecture.

Architecture

Overall Skylake builds upon Intel's previous microarchitecture, Broadwell, but includes a more beefed up front end, more optimized execution engine, and numerous number of smaller enhancements. Intel designed Skylake to encompass a wide range of devices and applications with a large emphasis on mobile with models ranging from as low as 4.5 W to as high as 100 W.

Key changes from Broadwell

• 8x performance/watt over Nehalem (Up from 3.5x in Haswell)
• Bus/Interface to Chipset
  • DMI 3.0 (from 2.0)
    • Skylake S and Skylake H cores, connected by 4-lane DMI 3.0
    • Skylake Y and Skylake U cores have chipset in the same package (simplified OPIO)
    • Increase in transfer rate from 5.0 GT/s to 8.0 GT/s (~3.93GB/s up from 2GB/s) per lane
    • Limits motherboard trace design to 7 inches max from (down from 8) from the CPU to chipset
• Front End
  • Larger legacy pipeline delivery (5 µOPs, up from 4)
  • Larger IDQ delivery (6 µOPs, up from 4)
  • 2.28x larger allocation queue (64/thread, up from 28/thread)
  • Improved branch prediction unit
• Execution Engine
  • Larger re-order buffer (224 entries, up from 192)
  • Larger scheduler (97 entries, up from 64)
    • Larger Integer Register File (180 entries, up from 160)
  • Larger store buffer (56 entries, up from 42)
• Memory
  • Support for faster DDR-2400 memory
  • L2$ was changed from 8-way to 4-way set associative
  • L3$ re-gained 512 KiB/core (See §eDRAM architectural changes for the reason)
  • A new coherent cache fabric implementation
    • doubles the throughput of the last level cache (LLC, L3$ in this case) miss handling
    • 50% improvement in bandwidth/watt
    • new eDRAM cache architecture for higher bandwidth
• TLBs
  • ITLB
    • 4 KiB page translations was changed from 4-way to 8-way associative
  • STLB
    • 4 KiB + 2 MiB page translations was changed from 6-way to 12-way associative
• Electrical
  • The fully integrated voltage regulator (FIVR) is moved back to the motherboard
    • Originally intended to be a cost-cutting measure by moving the FIVR on-die as well as making it more efficient, the move resulted in unintentionally making the FIVR the limiting factor when it came to overclocking.
• Testability
  • New support for Direct Connect Interface (DCI), a new debugging transport protocol designed to allow debugging of closed cases (e.g. laptops, embedded) by accessing things such as JTAG through any USB 3 port.

CPU changes

• Most ALU operations have 4 op/cycle 1 for 8 and 32-bit registers. 64-bit ops are still limited to 3 op/cycle. (16-bit throughput varies per op, can be 4, 3.5 or 2 op/cycle).
• MOVSX and MOVZX have 4 op/cycle throughput for 16->32 and 32->64 forms, in addition to Haswell's 8->32, 8->64 and 16->64 bit forms.
• ADC and SBB have throughput of 1 op/cycle, same as Haswell.
• Vector moves have throughput of 4 op/cycle (move elimination).
• Not only zeroing vector vpXORxx and vpSUBxx ops, but also vPCMPxxx on the same register, have throughput of 4 op/cycle.
• Vector ALU ops are often "standardized" to latency of 4. for example, vADDPS and vMULPS used to have L of 3 and 5, now both are 4.
• Fused multiply-add ops have latency of 4 and throughput of 0.5 op/cycle.
• Throughput of vADDps, vSUBps, vCMPps, vMAXps, their scalar and double analogs is increased to 2 op/cycle.
• Throughput of vPSLxx and vPSRxx with immediate (i.e. fixed vector shifts) is increased to 2 op/cycle.
• Throughput of vANDps, vANDNps, vORps, vXORps, their scalar and double analogs, vPADDx, vPSUBx is increased to 3 op/cycle.
• vDIVPD, vSQRTPD have approximately twice as good throughput: from 8 to 4 and from 28 to 12 cycles/op.
• Throughput of some MMX ALU ops (such as PAND mm1, mm2) is decreased to 2 or 1 op/cycle (users are expected to use wider SSE/AVX registers instead).

New GPU Features & Changes

• Adaptive scalable texture compression (ASTC)
• 16x multi-sample anti-aliasing (MSAA)
• Post depth test coverage mask
• Floating point atomics (min/max/cmpexch)
• Min/max texture filtering
• Multi-plane overlays

eDRAM architectural changes

In Broadwell, the eDRAM was statically attached to the LLC (last level cache, L3$), effectively stealing half a Mebibyte per core in the process, but behaving as an architectural true level 4 cache. This was fundamentally changed in Skylake. In Skylake, Intel removed the eDRAM from the LLC to its own array, re-freeing the 512 KiB (hence the 1.5 MiB/core in Broadwell and 2 MiB back in Skylake), but also removing the undesired dependency between the capacity of the eDRAM and the number of cores. Skylake's cache is effectively no longer a true level 4 cache but rather a memory side cache. This has a number of benefits such as that each and every memory access that goes through the memory controller gets looked up in the eDRAM. On a satisfied hit, the value is obtained from there. On a miss, a value gets allocated and stored in the eDRAM (subject to a number of restrictions, for example no I/O devices requests do not get cached on the eDRAM).

Skylake vs Broadwell eDRAM Architecture
Broadwell	Skylake

The new eDRAM changes mean it's no longer architectural - capable of caching any data (including "unreachable memory", display engines, effectively any memory transfer not bound by software restrictions) and is entirely invisible to software (one exception noted later) in terms of coherency (note that no flushing is thus necessary to maintain coherency), ordering, or other organizational details. For optimal graphics performance, the graphics driver may decide to limit certain memory accesses to only the eDRAM, only the LLC, or in both of them.

Graphics

• Improved underlying implementation of the memory QoS for higher resolution displays and the integrated image signal processor (ISP)
  • Allow for higher concurrent bandwidth
• Skylake retires VGA support, multi-monitor support for up to 3 displays via HDMI 1.4, DP 1.2, and eDP 1.3 interfaces.
• Direct X 12
• OpenCL 2.0
• OpenGL 4.4
• Up to 24 EUs GT2 (same as Haswell); 48 EUs for GT3, and up to 72 EUs on Iris Pro Graphics
  • 1,152 GFLOPS

IGP	Execution Units	GT	eDRAM	Series (Y/U/H/S)
HD Graphics	12	2+1	-	Y
HD Graphics 510	12	2+2	-	U/S
HD Graphics 515	24	2+2	-	Y
HD Graphics 520	24	4+2 2+2	-	U
HD Graphics 530	24	4+2 2+2	-	H/S
HD Graphics P530	24	4+2	-	H
Iris Graphics 540	48	2+3e	64 MiB	U
Iris Graphics 550	48	2+3e	64 MiB	U
Iris Pro Graphics 580	72	4+4e	128 MiB	H

New instructions

Main article: See §Added instructions for the complete list

Skylake introduced a number of new instructions:

• SGX - Software Guard Extensions
• MPX -Memory Protection Extensions
• AVX-512 - Advanced Vector Extensions 512 (Only on high-end Xeon models (SKX))

"Speed Shift" (new power management)

Intel introduced Speed Shift with Skylake, a new methodology for quickly alternating core frequencies in response to power loads. Intel introduced a new unit called PCU (Package Control Unit) which is effectively a full fledged microcontroller (containing power management logic and firmware) that collects and tracks many internal SoC statistics as well as external power telemetry (e.g. Psys and iMon). PCU is also capable of interfacing with the OS, BIOS, and DPTF. Speed Shift improves the performance of frequency shifting by off-loading the control from the operating system to the PCU.

Speed Shift effectively eliminates the need for the OS to manages the P-states - though it does have the final (unless special exceptions occur such as thermal throttling). Intel calls this "autonomous P-state", allowing Speed Shift to kick in in a matter of just ~1 millisecond (whereas the operating system-based p-states control can be as slow as 30 ms). Speed Shift effectively reduces hitting peak frequency in around ~30 ms from over 100 ms (OS-based implementation as before).

Power of System (Psys)

Psys (Power of System) is a way for the PCU to monitor the performance and the total platform power provided to the chip. The chip uses a number of autonomous algorithms (one for "Low Range" and one for "High Range"). The Low Range algorithm frequency is lowered to conserve energy. Algorithm is capable of overriding the low P state - a state calculated ever millisecond based on the active workload and system characteristics. The High Range algorithm deals with elevating frequency for the benefit of increase performance (at the cost of increase energy/inefficiency). The exact ratio of ΔPower/ΔPerformance ≤ αPreference can be finely controlled via the OS and user preferences.

Block Diagram

Memory Hierarchy

Other than a few organizational changes (e.g. L2$ went from 8-way to 4-way set associative), the overall memory structure is identical to Broadwell/Haswell.

• Cache
  • L1I Cache:
    • 32 KiB 8-way set associative
      • 64 B line size
      • Write-back policy
      • shared by the two threads, per core
  • L1D Cache:
    • 32 KiB 8-way set associative
    • 64 B line size
    • shared by the two threads, per core
    • 4 cycles for fastest load-to-use
    • 64 Bytes/cycle load bandwidth
    • 32 Bytes/cycle store bandwidth
    • Write-back policy
  • L2 Cache:
    • unified, 256 KiB 4-way set associative
    • 12 cycles for fastest load-to-use
    • 64B/cycle bandwidth to L1$
    • Write-back policy
  • L3 Cache:
    • Up to 2 MiB
    • Per core
    • Up to 16-way set associative
    • Write-back policy
  • L4 Cache:
    • 128 MiB
    • Per package
    • Only on the Iris Pro GPUs

Skylake TLB consists of dedicated level one TLB for instruction cache and another one for data cache. Additionally there is a unified second level TLB.

• TLBs:
  • ITLB
    • 4 KiB page translations:
      • 128 entries; 8-way set associative
      • dynamic partition; divided between the two threads
    • 2 MiB / 4 MiB page translations:
      • 8 entries; fully associative
      • Duplicated for each thread
  • DTLB
    • 4 KiB page translations:
      • 64 entries; 4-way set associative
      • fixed partition; divided between the two threads
    • 2 MiB / 4 MiB page translations:
      • 32 entries; 4-way set associative
      • fixed partition
    • 1G page translations:
      • 4 entries; 4-way set associative
      • fixed partition
  • STLB
    • 4 KiB + 2 MiB page translations:
      • 1536 entries; 12-way set associative
      • fixed partition
    • 1 GiB page translations:
      • 16 entries; 4-way set associative
      • fixed partition

Pipeline

This section is empty; you can help add the missing info by editing this page.

Die

Quad-core Skylake die:

Added instructions

SGX - Software Guard Extensions

MPX - Memory Protection Extensions

AVX-512 - Advanced Vector Extensions 512; These instructions can only be found on selected high-end Xeon models (codename SKX)

Cores

This section is empty; you can help add the missing info by editing this page.

All Skylake Chips

Documents

• 6th Gen Intel® Core™ Mobile Processor Family: Platform Brief
• 6th Gen Intel® Core™ processor family and Intel® Xeon® processors Factsheet
• 6th Gen Intel® Core™ Processors: Y-series, U-series, and H-series Product Brief
• 6th Gen Intel® Core™ vPro™ Processor Family Product Brief
• 6th Generation Intel® Core™ Desktop Processors i7-6700K and i5-6600K Product Brief