Semiconductor & Computer Engineering
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Difference between revisions of "intel/microarchitectures/ice lake (client)"
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| designer = Intel | | designer = Intel | ||
| manufacturer = Intel | | manufacturer = Intel | ||
| − | | introduction = | + | | introduction = 2018 |
| phase-out = | | phase-out = | ||
| − | | process = | + | | process = 10 nm |
| succession = Yes | | succession = Yes | ||
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| successor link = intel/microarchitectures/tigerlake | | successor link = intel/microarchitectures/tigerlake | ||
}} | }} | ||
| − | '''Icelake''' is a planned [[microarchitecture]] by [[Intel]] as a successor to {{\\|Cannonlake}}. Icelake is expected to be fabricated using a | + | '''Icelake''' is a planned [[microarchitecture]] by [[Intel]] as a successor to {{\\|Cannonlake}}. Icelake is expected to be fabricated using a [[10 nm process]]. |
Revision as of 03:33, 3 August 2016
| Edit Values | |
| Icelake µarch | |
| General Info |
Icelake is a planned microarchitecture by Intel as a successor to Cannonlake. Icelake is expected to be fabricated using a 10 nm process.
Facts about "Ice Lake (client) - Microarchitectures - Intel"
| codename | Ice Lake (client) + |
| core count | 2 + and 4 + |
| designer | Intel + |
| first launched | May 27, 2019 + |
| full page name | intel/microarchitectures/ice lake (client) + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Ice Lake (client) + |
| pipeline stages (max) | 19 + |
| pipeline stages (min) | 14 + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |