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|successor=Tanner Ridge
 
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|successor link=intel/microarchitectures/tanner_ridge
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|successor link=intel/cores/tanner_ridge
 
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'''Snow Ridge''' ('''SNR''') is a [[10 nm]] [[microarchitecture]] for servers and edge computing designed by [[Intel]]. SNR is planned to be introduced in late 2019.
 
'''Snow Ridge''' ('''SNR''') is a [[10 nm]] [[microarchitecture]] for servers and edge computing designed by [[Intel]]. SNR is planned to be introduced in late 2019.
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== Architecture ==
 
== Architecture ==
−
{{expand list}}
+
=== Jacobsville platform ===
 +
:(Snow Ridge / Parker Ridge)
 +
 
 +
The Snow Ridge System-on-a-Chip (SoC) product family is [[Intel]]’s next generation of communication processors designed in [[Intel]]’s [[10 nm]] process technology. The three major subsystems in this highly-integrated SoC are the Central Processing Unit (CPU) Complex, the Platform Control Hub (PCH), and the Network Accelerator Complex (NAC).
 +
 
 +
The CPU Complex contains up to 24 next-generation 64-bit Intel Atom processor cores (code name Tremont). The PCH is architected with a rich set of interconnect technologies. The NAC includes technologies for security and packet
 +
processing. The SoC architecture is highly scalable and efficient, providing a unified solution across an array of products.
 +
 
 +
=== Features ===
 +
* Up to 24 [[Intel Atom]] processor cores (code name {{intel|Tremont|l=arch}}) at up to 2.2 GHz
 +
* Mid-Level Cache (MLC) and Last Level Cache (LLC), including memory and cache
 +
* Quality of Service (QoS):
 +
:• 4.5 MB of MLC per four-core cluster, for a total of 27 MB for 6 clusters
 +
:• 2.5 MB of LLC per tile, for a total of 15 MB for 6 tiles
 +
* Integrated Memory Controller (IMC) that provides up to two 72-bit DDR4 interfaces (64-bit data + 8-bit Error Correcting Code (ECC)) and operating up to 2933 MT/s
 +
* Network Accelerator Complex (NAC) with high performance, programmable, packet-processing acceleration technology, including:
 +
:• Network Interface and Scheduler (NIS, code name ''Columbia Park''), with nine levels of hierarchical scheduling
 +
:• Flexible Packet Processor and Switch (FPPS, code name ''Highland Park'' (SKU dependent)), leveraging high-performance cut-through architecture
 +
:• Intel QuickAssist Technology (Intel QAT) v1.8 (SKU dependent), which performs security and compression acceleration
 +
 
 +
== Intel Atom Lines ==
 +
{{see also|Intel Atom|Intel|Core|intel/cpuid}}
 +
{| class="wikitable mw-datatable" style="margin:0.5em auto; text-align:center; min-width:70em;"
 +
|+ [[Intel Atom]] • {{intel|Roadmap}}
 +
|-
 +
! rowspan="2" | Fabri-<br>cation<br>process
 +
! rowspan="2" | Micro-<br>archi-<br>tecture
 +
! rowspan="2" | Release<br>date
 +
! colspan="8" | Processors / SoCs
 +
|-
 +
! Mobile
 +
! Tablet
 +
! Netbook
 +
! Nettop
 +
! Embedded
 +
! Server
 +
! <abbr title="Consumer Electronics">CE</abbr>
 +
|-
 +
| [[10 nm]]
 +
| {{intel|Tremont|l=arch}}
 +
| [[2020]]
 +
|
 +
| {{intel|Lakefield|l=arch}} <br>(hybrid)
 +
| colspan="3" | {{intel|Lakefield|l=arch}} (hybrid) <br>{{intel|Elkhart Lake|l=core}} <br>{{intel|Jasper Lake|l=core}}
 +
| {{intel|Jacobsville|l=platform}} platform: <br>{{intel|Parker Ridge|l=arch}} <br>{{intel|Snow Ridge|l=arch}}
 +
|
 +
|-
 +
| [[Intel]] [[7 nm]]
 +
| {{intel|Gracemont|l=arch}}
 +
| [[2021]]
 +
|
 +
|
 +
| colspan="3" | {{intel|Alder Lake|l=arch}} (hybrid) <br>{{intel|Alder Lake S|l=core}} (N/P/M) <br>{{intel|Raptor Lake|l=arch}} (S) (hybrid)
 +
| {{intel|Tanner Ridge|l=arch}}
 +
|
 +
|-
 +
| [[Intel]] [[7 nm]]
 +
| rowspan="3" | {{intel|Crestmont|l=arch}}
 +
| rowspan=2 | [[2023]]
 +
|
 +
|
 +
| colspan="3" rowspan="2" | {{intel|Meteor Lake|l=arch}} (hybrid)
 +
| {{intel|Grand Ridge|l=arch}}
 +
|
 +
|-
 +
| [[TSMC]] N6<br>[[6 nm]]
 +
|
 +
|
 +
|
 +
|
 +
|-
 +
| [[Intel]] [[3 nm]]
 +
| [[2024]]
 +
|
 +
|
 +
| colspan="3" |
 +
| {{intel|Sierra Forest|l=arch}}
 +
|
 +
|-
 +
| rowspan="3" | [[TSMC]] <br>N3B
 +
| rowspan="3" | [[Skymont]]
 +
| rowspan="3" | [[2024]]
 +
|
 +
|
 +
| colspan="3" | {{intel|Lunar Lake|l=arch}} (hybrid)
 +
|
 +
|
 +
|-
 +
|
 +
|
 +
| colspan="3" | {{intel|Arrow Lake|l=arch}} (hybrid)
 +
|
 +
|
 +
|-
 +
|
 +
|
 +
| colspan="3" | {{intel|Twin Lake|l=arch}} (E-cores, BGA)
 +
|
 +
|
 +
|-
 +
| [[Intel]] 18A
 +
| {{intel|Darkmont|l=arch}}
 +
| [[2025]]
 +
|
 +
|
 +
| colspan="3" |
 +
| {{intel|Clearwater Forest|l=arch}}
 +
|
 +
|-
 +
|}

Latest revision as of 20:11, 19 December 2025

Edit Values
Snow Ridge µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
Introduction2019
Process10 nm
Instructions
ISAx86-64
Succession

Snow Ridge (SNR) is a 10 nm microarchitecture for servers and edge computing designed by Intel. SNR is planned to be introduced in late 2019.

Process Technology[edit]

Snow Ridge is planned for Intel's 10 nm process.

Architecture[edit]

Jacobsville platform[edit]

(Snow Ridge / Parker Ridge)

The Snow Ridge System-on-a-Chip (SoC) product family is Intel’s next generation of communication processors designed in Intel’s 10 nm process technology. The three major subsystems in this highly-integrated SoC are the Central Processing Unit (CPU) Complex, the Platform Control Hub (PCH), and the Network Accelerator Complex (NAC).

The CPU Complex contains up to 24 next-generation 64-bit Intel Atom processor cores (code name Tremont). The PCH is architected with a rich set of interconnect technologies. The NAC includes technologies for security and packet processing. The SoC architecture is highly scalable and efficient, providing a unified solution across an array of products.

Features[edit]

  • Up to 24 Intel Atom processor cores (code name Tremont) at up to 2.2 GHz
  • Mid-Level Cache (MLC) and Last Level Cache (LLC), including memory and cache
  • Quality of Service (QoS):
• 4.5 MB of MLC per four-core cluster, for a total of 27 MB for 6 clusters
• 2.5 MB of LLC per tile, for a total of 15 MB for 6 tiles
  • Integrated Memory Controller (IMC) that provides up to two 72-bit DDR4 interfaces (64-bit data + 8-bit Error Correcting Code (ECC)) and operating up to 2933 MT/s
  • Network Accelerator Complex (NAC) with high performance, programmable, packet-processing acceleration technology, including:
• Network Interface and Scheduler (NIS, code name Columbia Park), with nine levels of hierarchical scheduling
• Flexible Packet Processor and Switch (FPPS, code name Highland Park (SKU dependent)), leveraging high-performance cut-through architecture
• Intel QuickAssist Technology (Intel QAT) v1.8 (SKU dependent), which performs security and compression acceleration

Intel Atom Lines[edit]

See also: Intel Atom, Intel, Core, and intel/cpuid
Intel Atom • Roadmap
Fabri-
cation
process 		Micro-
archi-
tecture 		Release
date 		Processors / SoCs
Mobile Tablet Netbook Nettop Embedded Server CE
10 nm Tremont 2020 Lakefield
(hybrid) 		Lakefield (hybrid)
Elkhart Lake
Jasper Lake 		Jacobsville platform:
Parker Ridge
Snow Ridge
Intel 7 nm Gracemont 2021 Alder Lake (hybrid)
Alder Lake S (N/P/M)
Raptor Lake (S) (hybrid) 		Tanner Ridge
Intel 7 nm Crestmont 2023 Meteor Lake (hybrid) Grand Ridge
TSMC N6
6 nm
Intel 3 nm 2024 Sierra Forest
TSMC
N3B 		Skymont 2024 Lunar Lake (hybrid)
Arrow Lake (hybrid)
Twin Lake (E-cores, BGA)
Intel 18A Darkmont 2025 Clearwater Forest
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/snow_ridge&oldid=104066"
Facts about "Snow Ridge - Microarchitectures - Intel"
RDF feed
codenameSnow Ridge +
designerIntel +
first launched2019 +
full page nameintel/microarchitectures/snow ridge +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameSnow Ridge +
process10 nm (0.01 μm, 1.0e-5 mm) +