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Difference between revisions of "via technologies"
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* {{centtech|Samuel|l=arch}} ([[2000]]) | * {{centtech|Samuel|l=arch}} ([[2000]]) | ||
* {{via|Samuel 2|l=arch}} ([[VIA]]) ([[2001]]) | * {{via|Samuel 2|l=arch}} ([[VIA]]) ([[2001]]) | ||
+ | * [[Centaur Technology|Centaur]] {{centtech|CHA|l=arch}} (CNS) ([[2019]]) | ||
:. | :. | ||
− | :;[[VIA]] | + | :;[[VIA]] Technologies |
{{collist | {{collist | ||
| count = 3 | | count = 3 | ||
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* {{via|Isaiah|l=arch}} ([[2008]]) | * {{via|Isaiah|l=arch}} ([[2008]]) | ||
* {{via|Isaiah II|l=arch}} ([[2014]]) | * {{via|Isaiah II|l=arch}} ([[2014]]) | ||
− | * {{ | + | * [[Centaur Technology|Centaur]] {{centtech|CHA|l=arch}} (CNS) ([[2019]]) |
}} | }} | ||
+ | |||
+ | === [[VIA]] Microarchitectures === | ||
+ | :;CPU | ||
+ | <table class="wikitable sortable"> | ||
+ | <tr><th colspan="12" style="background:#D6D6FF;">VIA Microarchitectures</th></tr> | ||
+ | <tr><th colspan="6">General</th><th colspan="5">Details</th></tr> | ||
+ | <tr><th>µarch</th><th>Type</th><th>ISA</th><th>Manuf</th><th>Introduction</th><th>Designer</th><th>[[technology node|Process]]</th><th>Cores</th><th colspan="3">Pipeline<br>Num•Min•Max</th></tr> | ||
+ | {{#ask: | ||
+ | [[instance of::microarchitecture]] [[designer::VIA Technologies||Cyrix||Centaur Technology]] <!--[[microarchitecture_type::~*]]--> | ||
+ | |?full_page_name | ||
+ | |?name | ||
+ | |?microarchitecture_type | ||
+ | |?instruction_set_architecture | ||
+ | |?manufacturer | ||
+ | |?first launched | ||
+ | |?designer | ||
+ | |?process | ||
+ | |?core count | ||
+ | |?pipeline stages | ||
+ | |?pipeline stages (min) | ||
+ | |?pipeline stages (max) | ||
+ | |sort=name<!--first launched--> | ||
+ | |order=ascending | ||
+ | |format=template | ||
+ | |template=proc table 2 | ||
+ | |userparam=12 | ||
+ | |valuesep=, | ||
+ | |mainlabel=- | ||
+ | }} | ||
+ | </table> | ||
== See also == | == See also == | ||
* [[Cyrix]] | * [[Cyrix]] | ||
* [[Centaur Technology]] ([[IDT]]) | * [[Centaur Technology]] ([[IDT]]) |
Latest revision as of 06:40, 13 May 2025
VIA Technologies | |
![]() | |
Type | Subsidiary |
Founded | 1987 Fremont, California |
Founder | Cher Wang |
Headquarters | New Taipei City, Taiwan |
Website | http://www.viatech.com/ |
VIA Technologies, Inc. is Taiwanese-American fabless semiconductor company that develops microprocessors, memory, and chipsets for AI, IoT, and computer vision applications.
MPU Families[edit]
Microarchitectures[edit]
CPU:
- .
- VIA Technologies
VIA Microarchitectures[edit]
- CPU
VIA Microarchitectures | |||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|
General | Details | ||||||||||
µarch | Type | ISA | Manuf | Introduction | Designer | Process | Cores | Pipeline Num•Min•Max | |||
CHA | CPU | x86-64 | TSMC | Centaur Technology | 16 nm 0.016 μm 1.6e-5 mm | 8 | 20 | 22 | |||
Esther | CPU | x86-32 | TSMC | VIA Technologies | 90 nm 0.09 μm 9.0e-5 mm | 1 | 16 | ||||
Ezra | CPU | x86-32 | TSMC | VIA Technologies | 130 nm 0.13 μm 1.3e-4 mm | 1 | 12 | ||||
Isaiah | CPU | x86-64 | Fujitsu, TSMC | VIA Technologies | 65 nm 0.065 μm , 40 nm6.5e-5 mm 0.04 μm 4.0e-5 mm | 2, 4 | |||||
Isaiah II | CPU | x86-64 | TSMC | VIA Technologies | 28 nm 0.028 μm 2.8e-5 mm | 2, 4 | |||||
Joshua | CPU | x86-32 | Texas Instruments | Cyrix | 180 nm 0.18 μm 1.8e-4 mm | 1 | 7 | ||||
Nehemiah | CPU | x86-32 | TSMC | VIA Technologies | 130 nm 0.13 μm 1.3e-4 mm | 1 | 16 | ||||
Samuel | CPU | x86-32 | TSMC | Centaur Technology | 180 nm 0.18 μm 1.8e-4 mm | 1 | 12 | ||||
Samuel 2 | CPU | x86-32 | TSMC | VIA Technologies | 150 nm 0.15 μm 1.5e-4 mm | 1 | 12 |
See also[edit]
Facts about "VIA Technologies"
company type | subsidiary + |
founded | 1987 + |
founded location | Fremont, California + |
founder | Cher Wang + |
full page name | via technologies + |
headquarters | New Taipei City, Taiwan + |
instance of | semiconductor company + |
name | VIA Technologies + |
website | http://www.viatech.com/ + |
wikidata id | Q633839 + |